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user?s manual v850/sa1 32-bit single-chip microcontroller hardware pd703014a pd70f3015b pd703014ay pd70f3015by pd703014b pd70f3017a pd703014by pd70f3017ay pd703015a pd703015ay pd703015b pd703015by pd703017a pd703017ay printed in japan document no. u12768ej4v1ud00 (4th edition) date published august 2005 n cp(k) ?
user?s manual u12768ej4v1ud 2 [memo]
user?s manual u12768ej4v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
user?s manual u12768ej4v1ud 4 windows is either a registered tradem ark or a trademark of microsoft cor poration in the united states and/or other countries. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of august, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u12768ej4v1ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
user?s manual u12768ej4v1ud 6 major revisions in this edition (1/2) page description throughout addition of pd703014b, 703014by, 703015b, 703015by, 70f3015b, and 70f3015by deletion of pd703014agc, 703014aygc, 703015agc, and 703015aygc p. 27 addition of table 1-1 list of v850/sa1 products p. 28 addition of description to mini mum instruction execution time in 1.2 features p. 30 deletion and addition of products in 1.4 ordering information p. 31 deletion and addition of products in 1.5 pin configuration p. 35 deletion of description in 1.6.2 (2) bus control unit (bcu) p. 38 addition of table 2-1 pin i/o buffer power supplies p. 43 modification of description in table 2-2 operating states of pins in each operating mode p. 49 modification of description in 2.3 (7) p60 to p65 (port 6) p. 53 addition of 2.3 (13) clkout (clock out) p. 55 addition and modification of description in 2.4 pin i/o circuits and recommended connection of unused pins p. 58 modification of 2.5 pin i/o circuits p. 59 addition of description to mini mum instruction execution time in 3.1 features p. 63 change of description in 3.2.2 (2) program status word (psw) p. 80 modification of figure 3-16 recommended memory map p. 81 addition of description in 3.4.8 peripheral i/o registers p. 86 addition and modifica tion of description in 3.4.9 specific registers p. 113 addition of description in 5.2.4 noise elimination of external interrupt request input pin p. 114 addition of description in 5.2.5 edge detection function of external interrupt request input pin p. 122 addition to cautions in 5.3.4 interrupt control register (xxicn) p. 125 addition of caution in 5.3.5 in-service priority register (ispr) p. 136 addition of 5.8.1 interrupt request valid timing after ei instruction p. 137 addition of 5.9 bit manipulation instruction of inte rrupt control register during dma transfer p. 138 modification of description in 6.1 (1) main clock oscillator p. 138 modification of description in 6.1 (2) subclock oscillator p. 139 modification of figure 6-1 clock generator p. 140 addition to notes in 6.3.1 (1) processor clock control register (pcc) p. 141 modification of description in 6.3.1 (1) (b) example of subclock operation main clock operation setup p. 142 addition to notes and cautions in 6.3.1 (2) power save control register (psc) p. 148 modification of description in 6.4.4 (1) settings and operating states p. 151 addition of 6.6 notes on power save function p. 156 modification of caution in 7.1.3 (2) capture/compare registers 00, 10 (cr00, cr10) p. 157 modification of caution in 7.1.3 (3) capture/compare registers 01, 11 (cr01, cr11) p. 185 change of figure 7-27 data hold timing of capture register p. 185 addition of 7.2.7 (6) (c) one-shot output function p. 189 addition of 7.3.1 outline the mark shows major revised points.
user?s manual u12768ej4v1ud 7 major revisions in this edition (2/2) page description p. 196 change of caution in 7.3.4 (2) 8-bit timer mode control registers 2 to 5 (tmc2 to tmc5) p. 242 modification of description in 10.3.2 (3) iic clock select register 0 (iiccl0), iic function expansion register 0 (iicx0) pp. 295 to 299 addition of figures 10-25 to 10-29 p. 313 modification in 11.3 (1) a/d converter mode register (adm) p. 314 addition of table 11-2 a/d conversion time selection p. 326 addition of 11.6 how to read a/d converter characteristics table p. 330 change of description in 12.1 functions p. 330 deletion of 12.2 transfer completion interrupt request and addition of 12.2 features p. 331 addition of 12.3 configuration p. 333 addition of figure 12-2 correspondence between dran setting value and internal ram (4 kb) p. 334 addition of figure 12-3 correspondence between dran setting value and internal ram (8 kb) p. 338 addition of 12.5 operations p. 339 addition of 12.6 cautions p. 340 addition of 13.2 features p. 342 addition of 13.3 (2) output latch p. 345 modification of description in 13.5 usage p. 347 addition of description in 13.7 cautions p. 348 addition of table 14-1 pin i/o buffer power supplies p. 380 addition of caution in 14.2.8 (1) function of p9 pins p. 396 addition of 14.4 operation of port function p. 398 addition of caution in chapter 16 flash memory p. 398 change of description in 16.1.1 erasing unit p. 400 addition of figure 16-1 wiring example of v850/sa 1 flash writing adapter (fa-100gc-8eu) p. 401 addition of table 16-1 wiring table of v850/sa1 flash writing adapter (fa-100gc-8eu) p. 402 addition of figure 16-2 wiring example of v850/sa 1 flash writing adapter (fa-121f1-ea6) p. 403 addition of table 16-2 wiring table of v850/sa1 flash writing adapter (fa-121f1-ea6) p. 413 addition of 16.7 flash memory programming by self-programming p. 434 addition of chapter 17 electrical specifications p. 460 addition of chapter 18 package drawings p. 462 addition of chapter 19 recommended soldering conditions p. 466 addition of appendix a notes on target system design p. 468 addition of description in appendix b register index p. 486 addition of appendix e revision history major revisions in modifica tion version (u12768ej4v1ud00) throughout addition of lead-free products pd703014af1- -ea6-a, 703014ayf1- -ea6-a, 703014bbf1- -ea6-a, 703014bgc- -8eu-a, pd703014byf1- - ea6-a, 703014bygc- -8eu-a, 703015af1- -ea6-a, 703015ayf1- -ea6-a, pd703015bf1- -ea6-a, 703015bgc- -8eu-a, 703015byf1- -ea6-a, 703015bygc- -8eu-a, pd703017af1- -ea6-a, 703017agc- -8eu-a, 703017ayf1- -ea6-a, 703017aygc- -8eu-a, pd70f3015bf1-ea6-a, 70f3015bgc-8eu-a, 70f3015byf1-ea6-a, 70f3015bygc-8eu-a, pd70f3017af1-ea6-a, 70f3017agc-8eu-a, 70f3017ayf1-ea6-a, 70f3017aygc-8eu-a p.462 addition of lead-free products to chapter 19 recommended soldering conditions the mark shows major revised points.
user?s manual u12768ej4v1ud 8 introduction readers this manual is intended for users who wish to understand the functi ons of the v850/sa1 ( pd703014a, 703014ay, 703014b, 703014by 703015a, 703015ay, 703015b, 703015by, 703017a, 703017ay, 70f3015b, 70f3015 by, 70f3017a, 70f3017ay) and design application systems using the v850/sa1. purpose this manual is intended to give users an underst anding of the hardware func tions described in the organization below. organization the v850/sa1 user?s manual is divided into tw o parts: hardware (this manual) and architecture (v850 series user?s manual architecture). hardware architecture ? pin function ? cpu function ? on-chip peripheral function ? flash memory programming ? electrical specifications ? data type ? register set ? instruction format and instruction set ? interrupt and exception ? pipeline operation how to use this manual it is assumed that the reader of this m anual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to find out the details of a r egister whose name is known: refer to appendix b register index . to find out the details of a func tion, etc., whose name is known: refer to appendix d index . to understand the details of a instruction function: refer to v850 series user?s manual architecture available separately. how to read register formats: names of bits whose numbers are enclosed in a square are defined in the device file under reserved words. to understand the overall f unctions of the v850/sa1: read this manual in the order of the contents . to know the electrical spec ifications of the v850/sa1: refer to chapter 17 electrical specifications .
user?s manual u12768ej4v1ud 9 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for items marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefixes indicating power of 2 ( address space, memory capacity): k (kilo) ? 2 10 =1024 m (mega) ? 2 20 =1024 2 g (giga) ? 2 30 =1024 3
user?s manual u12768ej4v1ud 10 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850/sa1 document name document no. v850 series architecture user?s manual u10243e v850/sa1 application note u13851e v850/sa1 hardware user?s manual this manual v850 series flash memory self programming user?s manual u15673e documents related to developm ent tools (user?s manuals) document name document no. ie-703002-mc (in-circuit emulator) u11595e ie-703017-mc-em1 (in-circuit em ulator option board) u12898e operation u15024e c language u15025e project manager u15026e ca850 ver. 2.40 or later c compiler package assembly language u15027e id850 ver. 2.40 integrated debugger operation (windows? based) u15181e sm850 ver. 2.40 system simulator operation (windows based) u15182e sm850 ver. 2.00 or later system si mulator external part user open interface specifications u14873e basic u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e basic u13773e installation u13774e rx850 pro ver. 3.13 or later real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.0 system performance analyzer u14410e pg-fp3 flash memory programmer u13502e pg-fp4 flash memory programmer u15260e
user?s manual u12768ej4v1ud 11 contents chapter 1 introduction ...................................................................................................... ...........27 1.1 general .................................................................................................................... ..................27 1.2 features................................................................................................................... ..................28 1.3 applications ............................................................................................................... ...............30 1.4 ordering information ....................................................................................................... ........30 1.5 pin configuration .......................................................................................................... ...........31 1.6 function blocks ............................................................................................................ ...........34 1.6.1 internal block di agram ................................................................................................... .............. 34 1.6.2 inter nal uni ts........................................................................................................... ..................... 35 chapter 2 pin funct ions.................................................................................................... ............38 2.1 list of pin functions...................................................................................................... ..........38 2.2 pin states ................................................................................................................. .................43 2.3 description of pin functions ...................................... ......................................................... ...44 2.4 pin i/o circuits and recommended connection of unused pins.......................................55 2.5 pin i/o circuits........................................................................................................... ...............57 chapter 3 cpu funct ions .................................................................................................... ..........59 3.1 features................................................................................................................... ..................59 3.2 cpu register set........................................................................................................... ...........60 3.2.1 program r egister set..................................................................................................... ............... 61 3.2.2 system r egister set ...................................................................................................... ............... 62 3.3 operation modes ............................................................................................................ ..........65 3.4 address space .............................................................................................................. ...........66 3.4.1 cpu addr ess s pace ........................................................................................................ ............ 66 3.4.2 image .................................................................................................................... ...................... 67 3.4.3 wraparound of cp u address space.......................................................................................... .. 68 3.4.4 memo ry map ............................................................................................................... ................ 69 3.4.5 area ..................................................................................................................... ....................... 70 3.4.6 external expansion mode.................................................................................................. .......... 77 3.4.7 recommended use of address space ......................................................................................... 79 3.4.8 peripheral i/o registers ................................................................................................. .............. 81 3.4.9 specific regist ers....................................................................................................... .................. 86 chapter 4 bus control function.............................. .............................................................. .89 4.1 features................................................................................................................... ..................89 4.2 bus control pins and control register .................. ...............................................................89 4.2.1 bus c ontrol pins ......................................................................................................... .................. 89 4.2.2 contro l regi ster......................................................................................................... ................... 90 4.3 bus access ................................................................................................................ ..................90 4.3.1 number of access clocks .................................................................................................. .......... 90 4.3.2 bu s width................................................................................................................ ..................... 91
user?s manual u12768ej4v1ud 12 4.4 memory block function...................................................................................................... .....92 4.5 wait function .............................................................................................................. ..............93 4.5.1 programmable wait f unction ............................................................................................... .........93 4.5.2 external wait f unction ................................................................................................... ...............94 4.5.3 relationship between programm able wait and exte rnal wa it ....................................................... 94 4.6 idle state insertion function .............................................................................................. .....95 4.7 bus hold function.......................................................................................................... ..........96 4.7.1 outline of func tion...................................................................................................... ..................96 4.7.2 bus hol d proc edure ....................................................................................................... ..............97 4.7.3 operation in power save mode............................................................................................. .......97 4.8 bus timing ................................................................................................................. ...............98 4.9 bus priority ............................................................................................................... ............. 105 4.10 memory boundary operation conditions ................... ........................................................ 105 4.10.1 program space ........................................................................................................... ...............105 4.10.2 data space .............................................................................................................. ..................105 chapter 5 interrupt/exception processing func tion................................................. 106 5.1 outline .................................................................................................................... ................ 106 5.1.1 f eatur es ................................................................................................................. ...................106 5.2 non-maskable interr upts .................................................................................................... .. 109 5.2.1 oper ation................................................................................................................ ...................110 5.2.2 re store.................................................................................................................. ....................112 5.2.3 np flag.................................................................................................................. .....................113 5.2.4 noise elimination of exter nal interrupt reques t input pin ............................................................113 5.2.5 edge detection functi on of external interrupt request input pin ..................................................114 5.3 maskable interrupts........................................................................................................ ....... 115 5.3.1 oper ation................................................................................................................ ...................115 5.3.2 re store.................................................................................................................. ....................117 5.3.3 priorities of maskable in terrupts ........................................................................................ ........118 5.3.4 interrupt contro l register (xxicn) ....................................................................................... .........122 5.3.5 in-service priori ty register (ispr)...................................................................................... .........125 5.3.6 id flag .................................................................................................................. ......................126 5.3.7 watchdog timer mode register (wdtm) ....................................................................................12 6 5.4 software exceptions ........................................................................................................ ..... 127 5.4.1 oper ation................................................................................................................ ...................127 5.4.2 re store.................................................................................................................. ....................128 5.4.3 ep flag.................................................................................................................. .....................129 5.5 exception trap............................................................................................................. .......... 129 5.5.1 illegal opc ode definit ion ................................................................................................ .............129 5.5.2 oper ation................................................................................................................ ...................130 5.5.3 re store.................................................................................................................. ....................131 5.6 priority control ........................................................................................................... ........... 132 5.6.1 priorities of in terrupts and e xcepti ons.................................................................................. ......132 5.6.2 multiple interr upts ...................................................................................................... ................132 5.7 interrupt latency time..................................................................................................... ..... 135 5.8 periods in which interrupts are not acknowledge d......................................................... 135 5.8.1 interrupt request valid ti ming after ei instruct ion...................................................................... ..136
user?s manual u12768ej4v1ud 13 5.9 interrupt control register bit manipulation instructions during dma transfer.............137 chapter 6 clock generation function ................ ...............................................................138 6.1 general .................................................................................................................... ................138 6.2 configuration .............................................................................................................. ............139 6.3 clock output function...................................................................................................... .....139 6.3.1 control regist ers........................................................................................................ ................ 140 6.4 power save functions ....................................................................................................... ....143 6.4.1 g eneral .................................................................................................................. ................... 143 6.4.2 halt mode ................................................................................................................ ............... 144 6.4.3 idle mode ................................................................................................................ ................ 147 6.4.4 software stop mode ....................................................................................................... ........ 148 6.5 oscillation stabilization time ............................................................................................. ..150 6.6 cautions on power save function .............................. .........................................................151 chapter 7 timer/counter function ........................... .............................................................153 7.1 16-bit timers (tm0, tm1)................................................................................................... ....153 7.1.1 ou tline.................................................................................................................. ..................... 153 7.1.2 f uncti ons................................................................................................................ ................... 153 7.1.3 confi guratio n............................................................................................................ ................. 155 7.1.4 timer 0, 1 c ontrol regi sters............................................................................................. ........... 158 7.2 16-bit timer operation..................................................................................................... ......166 7.2.1 operation as inte rval timer (16 bi ts) .................................................................................... ...... 166 7.2.2 ppg output operat ion..................................................................................................... ........... 168 7.2.3 pulse width measur ement .................................................................................................. ....... 169 7.2.4 operation as ex ternal event count er ...................................................................................... ... 176 7.2.5 operation to output squar e wave .......................................................................................... .... 178 7.2.6 operation to output one-s hot pul se ....................................................................................... .... 179 7.2.7 c auti ons ................................................................................................................. ................... 184 7.3 8-bit timers (tm2 to tm5) .................................................................................................. ...189 7.3.1 ou tline.................................................................................................................. ..................... 189 7.3.2 f uncti ons................................................................................................................ ................... 189 7.3.3 confi guratio n............................................................................................................ ................. 190 7.3.4 timer n c ontrol r egister ................................................................................................. ............ 192 7.4 8-bit timer operation...................................................................................................... .......197 7.4.1 operation as interval timer (8-bit operat ion) ............................................................................ .. 197 7.4.2 operation as ex ternal event count er ...................................................................................... ... 200 7.4.3 operation as square wave output (8-bit resoluti on)................................................................... 201 7.4.4 operation as 8-bit pw m out put ............................................................................................ ..... 202 7.4.5 operation as inte rval timer (16 bi ts) .................................................................................... ...... 205 7.4.6 c auti ons ................................................................................................................. ................... 207 chapter 8 watch timer ...................................................................................................... ..........208 8.1 functions .................................................................................................................. ..............208 8.2 configuration .............................................................................................................. ............209 8.3 watch timer control register ..............................................................................................2 10
user?s manual u12768ej4v1ud 14 8.4 operation.................................................................................................................. .............. 211 8.4.1 operation as watch timer................................................................................................. ..........211 8.4.2 operation as interval timer .............................................................................................. ..........211 8.4.3 c auti ons ................................................................................................................. ...................212 chapter 9 watchdog timer ................................................................................................... .... 213 9.1 functions.................................................................................................................. .............. 213 9.2 configuration .............................................................................................................. ........... 215 9.3 watchdog timer control register ....................................................................................... 215 9.4 operation.................................................................................................................. .............. 218 9.4.1 operating as watchdog timer.............................................................................................. .......218 9.4.2 operating as interval timer .............................................................................................. ..........219 9.5 standby function control regist er ..................................................................................... 220 chapter 10 serial interface function ..................... .......................................................... 221 10.1 overview.................................................................................................................. ............... 221 10.2 3-wire serial i/o (csi0 to csi2) .......................................................................................... .. 221 10.2.1 confi guratio n ........................................................................................................... ..................222 10.2.2 csin cont rol regi sters .................................................................................................. ..............223 10.2.3 oper ati ons.............................................................................................................. ...................225 10.3 i 2 c bus (interface i 2 c) ............................................................................................................ 228 10.3.1 confi guratio n ........................................................................................................... ..................231 10.3.2 i 2 c control r egister s ............................................................................................................ .......233 10.3.3 i 2 c bus mode functi ons........................................................................................................... ...243 10.3.4 i 2 c bus definitions and control me thods .....................................................................................244 10.3.5 i 2 c interrupt r equest (int iic0) .................................................................................................. .251 10.3.6 interrupt request (intiic0) gener ation timing and wa it cont rol ..................................................269 10.3.7 address matc h detection method .......................................................................................... ....270 10.3.8 error detecti on......................................................................................................... ..................270 10.3.9 extens ion c ode .......................................................................................................... ................270 10.3.10 arbi tration ............................................................................................................ ......................271 10.3.11 wakeup functi on........................................................................................................ ................272 10.3.12 communicati on reserv ation .............................................................................................. .........273 10.3.13 c auti ons ............................................................................................................... .....................276 10.3.14 communica tion operat ions ............................................................................................... .........277 10.3.15 timing of dat a communi cation........................................................................................... ........279 10.4 asynchronous serial interface (uart0, uart1)....... ........................................................ 286 10.4.1 confi guratio n ........................................................................................................... ..................286 10.4.2 uartn cont rol regi sters ................................................................................................. ...........288 10.4.3 oper ati ons.............................................................................................................. ...................294 10.4.4 standby functi on........................................................................................................ ................307 chapter 11 a/d converter ................................................................................................... ...... 308 11.1 function.................................................................................................................. ................ 308 11.2 configuration ............................................................................................................. ............ 310 11.3 control registers......................................................................................................... .......... 312
user?s manual u12768ej4v1ud 15 11.4 operation................................................................................................................. ................316 11.4.1 basic operatio n ......................................................................................................... ................ 316 11.4.2 input voltage and conversion result..................................................................................... ...... 318 11.4.3 a/d converte r operati on m ode ............................................................................................ ...... 319 11.5 notes on using a/d converter.............................................................................................. 322 11.6 how to read a/d converter characteristics table... ..........................................................326 chapter 12 dma funct ions................................................................................................... .......330 12.1 functions ................................................................................................................. ...............330 12.2 features.................................................................................................................. .................330 12.3 configuration ............................................................................................................. .............331 12.4 control registers ......................................................................................................... ..........332 12.5 operation................................................................................................................. ................338 12.6 cautions .................................................................................................................. ................339 chapter 13 real-time output function (rto) ... ................................................................340 13.1 function .................................................................................................................. ................340 13.2 features.................................................................................................................. .................340 13.3 configuration ............................................................................................................. .............341 13.4 control registers ......................................................................................................... ..........343 13.5 usage..................................................................................................................... ..................345 13.6 operation................................................................................................................. ................346 13.7 cautions .................................................................................................................. ................347 chapter 14 port function ................................................................................................... .......348 14.1 port configuration........................................................................................................ ..........348 14.2 port pin function ......................................................................................................... ..........348 14.2.1 po rt 0 .................................................................................................................. ...................... 348 14.2.2 po rt 1 .................................................................................................................. ...................... 353 14.2.3 po rt 2 .................................................................................................................. ...................... 359 14.2.4 po rt 3 .................................................................................................................. ...................... 367 14.2.5 port s 4 and 5........................................................................................................... .................. 372 14.2.6 po rt 6 .................................................................................................................. ...................... 375 14.2.7 port s 7 and 8........................................................................................................... .................. 377 14.2.8 po rt 9 .................................................................................................................. ...................... 379 14.2.9 po rt 10 ................................................................................................................. ..................... 383 14.2.10 po rt 11 ............................................................................................................... ...................... 387 14.2.11 po rt 12 ................................................................................................................ ...................... 390 14.3 setting when port pin is used as alternate functi on........................................................393 14.4 operation of port function..................................... ........................................................... ....396 14.4.1 writing dat a to i/o port ................................................................................................ .............. 396 14.4.2 reading data from i/o port.............................................................................................. .......... 396
user?s manual u12768ej4v1ud 16 chapter 15 reset function .................................................................................................. ..... 397 15.1 general ................................................................................................................... ................ 397 15.2 pin operations ............................................................................................................ ........... 397 chapter 16 flash memory .................................................................................................... ...... 398 16.1 features.................................................................................................................. ................ 398 16.1.1 eras ing uni t ............................................................................................................ ...................398 16.2 writing by flash programmer ...................................... ........................................................ 3 99 16.3 programming environment .................................................................................................. 4 04 16.4 communication system...................................................................................................... .. 404 16.5 pin connection ............................................................................................................ .......... 407 16.5.1 v pp pin ........................................................................................................................... ............407 16.5.2 serial in terface pin.................................................................................................... .................407 16.5.3 reset pin............................................................................................................... ..................409 16.5.4 port pin (includi ng nmi) ................................................................................................ .............409 16.5.5 other signal pins....................................................................................................... .................409 16.5.6 powe r suppl y............................................................................................................ .................409 16.6 programming method........................................................................................................ .... 410 16.6.1 flash memo ry control .................................................................................................... ............410 16.6.2 flash memory programmi ng m ode........................................................................................... .410 16.6.3 selection of communicati on m ode......................................................................................... ....411 16.6.4 communica tion co mmand................................................................................................... ......411 16.6.5 resour ces us ed.......................................................................................................... ...............412 16.7 flash memory programming by self-programming .. ........................................................ 413 16.7.1 outline of self-progr amming ............................................................................................. .........413 16.7.2 self-progr amming f unction ............................................................................................... .........414 16.7.3 outline of self-p rogramming in terface................................................................................... .....415 16.7.4 hardware envir onment .................................................................................................... ..........415 16.7.5 softwar e envir onment.................................................................................................... ............417 16.7.6 self-progra mming functi on num ber ........................................................................................ ...418 16.7.7 calling paramet ers ...................................................................................................... ..............419 16.7.8 contents of ram param eters .............................................................................................. ......420 16.7.9 errors during self-progr amming .......................................................................................... .......421 16.7.10 flash informa tion ...................................................................................................... .................421 16.7.11 ar ea num ber............................................................................................................ ..................422 16.7.12 flash programming mode c ontrol register (flpmc )..................................................................423 16.7.13 calling device in ternal pr ocessi ng ..................................................................................... ........425 16.7.14 flow of eras ing flash memory........................................................................................... .........428 16.7.15 successive writing flow................................................................................................ ..............429 16.7.16 internal verify flow................................................................................................... ...................430 16.7.17 flow of acquiri ng flash in formati on .................................................................................... ........431 16.7.18 self-progr amming lib rary ............................................................................................... ............432 chapter 17 electrical specifications ....................... .......................................................... 434 chapter 18 package drawings ................................................................................................ 460
user?s manual u12768ej4v1ud 17 chapter 19 recommended soldering conditions .. .........................................................462 appendix a notes on target system design.... ................................................................466 appendix b register index .................................................................................................. ........468 appendix c list of instruction sets ..................... ...............................................................47 3 appendix d index ............................................................................................................ ..................480 appendix e revision history ................................................................................................. ......486
user?s manual u12768ej4v1ud 18 list of figures (1/6) figure no. title page 3-1 cpu regi ster set .......................................................................................................... ..................................60 3-2 cpu addr ess s pace......................................................................................................... ...............................66 3-3 image on a ddress s pace .................................................................................................... ............................67 3-4 program space............................................................................................................. ...................................68 3-5 data space ................................................................................................................ ......................................68 3-6 memo ry map................................................................................................................ ....................................69 3-7 internal rom area (64 kb)................................................................................................. .............................70 3-8 internal rom area (128 kb)................................................................................................ ............................70 3-9 internal rom/internal flash memory area ( 256 kb) .......................................................................... .............71 3-10 internal ram area (4 kb) ................................................................................................. ...............................73 3-11 internal ram area (8 kb) ................................................................................................. ...............................73 3-12 on-chip pe ripheral i/o area.............................................................................................. ..............................74 3-13 external memory area (when expanded to 64 kb, 256 kb, or 1 mb) ........................................................... .75 3-14 external memory area (when expanded to 4 mb) ............................................................................. .............76 3-15 application ex ample of wrapar ound........................................................................................ ........................79 3-16 recommended memory map................................................................................................... ........................80 4-1 byte acce ss (8 bi ts)...................................................................................................... ...................................91 4-2 halfword a ccess (16 bits)................................................................................................. ...............................91 4-3 word acce ss (32 bi ts) ..................................................................................................... ................................91 4-4 memory space.............................................................................................................. ...................................92 4-5 wait contro l .............................................................................................................. .......................................94 4-6 example of inse rting wait states.......................................................................................... ...........................94 4-7 bus hold proc edure........................................................................................................ .................................97 4-8 memo ry r ead .............................................................................................................. ...................................98 4-9 memory write ............................................................................................................. ..................................102 4-10 bus ho ld ti ming .......................................................................................................... ..................................104 5-1 non-maskable in terrupt se rvicing.......................................................................................... ........................110 5-2 acknowledging non-ma skable interr upt r equest .............................................................................. ............111 5-3 reti instru ction proc essing ............................................................................................... ...........................112 5-4 np flag (n p) .............................................................................................................. ...................................113 5-5 maskable inte rrupt serv icing .............................................................................................. ...........................116 5-6 reti instru ction proc essing ............................................................................................... ...........................117 5-7 example of multiple interrupt servic ing .................................................................................. ......................119 5-8 example of servicing interr upt requests gener ated simu ltaneous ly.......................................................... ..121 5-9 interrupt dis able flag (id) ................................................................................................ .............................126 5-10 software exc eption proc essing ............................................................................................ .........................127 5-11 reti instru ction proc essing .............................................................................................. ............................128 5-12 ep fl ag ( ep)............................................................................................................. .....................................129
user?s manual u12768ej4v1ud 19 list of figures (2/6) figure no. title page 5-13 illegal opc ode ........................................................................................................... .................................... 129 5-14 exception trap proc essing................................................................................................ ............................ 130 5-15 reti instru ction proc essing .............................................................................................. ............................ 131 5-16 pipeline operation at in terrupt request acknowl edgement .................................................................. ........ 135 5-17 pipeline flow and interrupt request signal gener ation ti ming ............................................................. ....... 137 6-1 clock generat or ........................................................................................................... ................................. 139 6-2 oscillation st abilizati on time............................................................................................ ............................. 150 7-1 block diagram of tm0 and tm1 .............................................................................................. ...................... 154 7-2 control register settings when tmn operates as interval timer ............................................................. .... 166 7-3 configuration of interval timer ........................................................................................... ........................... 167 7-4 timing of interv al timer o peratio n ........................................................................................ ........................ 167 7-5 control register settings in ppg output operat ion ......................................................................... ............. 168 7-6 control register settings for pulse width measurement with free-runni ng counter and one capture regist er ....................................................................................................................... .................................. 169 7-7 configuration for pulse width measurement with fr ee-running c ounter ..................................................... 17 0 7-8 timing of pulse width m easurement with free-running counter and one captur e regist er ...................... 170 (with both e dges spec ified) .................................................................................................. ....................... 170 7-9 control register settings for measurement of two pulse widths wit h free-running counter ..................... 171 7-10 crn1 capture operation with rising edge specif ied........................................................................ ............ 172 7-11 timing of pulse width meas urement with free-running counter ( with both edges specifi ed) .................... 172 7-12 control register settings for pulse width measurement with free-runni ng counter and two capture regist ers ...................................................................................................................... ................................. 173 7-13 timing of pulse width measur ement with free-running counter and ....... two capture registers (with rising edge spec ifi ed) ................................................................................................................ ............................. 174 7-14 control register settings for pu lse width measurement by rest arting...................................................... ... 175 7-15 timing of pulse width measurement by restarting (with risi ng edge spec ified) ......................................... 175 7-16 control register settings in external event counter mode ................................................................. .......... 176 7-17 configuration of external ev ent c ounter .................................................................................. ..................... 177 7-18 timing of external event counter operation (with risi ng edge spec ified).................................................. .. 177 7-19 control register settings in square wave output mode..................................................................... .......... 178 7-20 timing of square wa ve output operat ion................................................................................... .................. 179 7-21 control register settings for one- shot pulse output with softwar e tri gger ................................................ . 180 7-22 timing of one-shot pulse out put operation with software tri gger .......................................................... .... 181 7-23 control register settings for one-s hot pulse output wit h external trigger ................................................ .. 182 7-24 timing of one-shot pulse ou tput operation with external tri gger (with rising e dge specif ied) .................. 183 7-25 start timing of 16- bit timer r egister n .................................................................................. ....................... 184 7-26 timing after changing compare regist er during timer c ount operat ion .................................................... 18 4
user?s manual u12768ej4v1ud 20 list of figures (3/6) figure no. title page 7-27 data hold timing of capture regist er ..................................................................................... ......................185 7-28 operation timi ng of ovfn flag ............................................................................................. ........................186 7-29 block diagram of tm2 to tm5 .............................................................................................. .........................190 7-30 timing of interv al timer o peratio n ....................................................................................... .........................197 7-31 timing of external event counter operation (when ris ing edge is set) ..................................................... .200 7-32 timing of square wa ve output operat ion ................................................................................... ..................201 7-33 timing of pwm ou tput ..................................................................................................... .............................203 7-34 timing of operation based on crn0 transit ion ............................................................................. ...............204 7-35 cascade connection mode with 16-bit re soluti on ........................................................................... .............206 7-36 start timi ng of ti mer n .................................................................................................. ................................207 7-37 timing after compare register c hanges during timer c ount operat ion .....................................................20 7 8-1 block diagram of watch timer .............................................................................................. ........................208 8-2 operation timing of wa tch timer/inte rval ti mer ............................................................................ ...............212 8-3 example of generation of watch timer interr upt request (intwt) (when inte rrupt period = 0.5 s) ...........212 9-1 block diagram of watchdog timer ........................................................................................... .....................213 10-1 block diagram of 3-wire se rial i/o ....................................................................................... .........................222 10-2 settings of csim n (operation stop m ode) .................................................................................. ..................225 10-3 settings of csimn (3-wire seri al i/o mode) ............................................................................... ...................226 10-4 timing of 3-wi re serial i/o mode......................................................................................... ..........................227 10-5 block diagram of i 2 c.............................................................................................................................. ........229 10-6 serial bus configuration example using i 2 c bus ..........................................................................................230 10-7 pin confi guration diagr am................................................................................................ .............................243 10-8 i 2 c bus?s serial data transfer timing............................................................................................ ................244 10-9 star t condi tion ......................................................................................................... ......................................244 10-10 a ddres s ................................................................................................................. ........................................245 10-11 transfer directi on specific ation ........................................................................................ .............................246 10-12 ac k si gnal .............................................................................................................. ......................................247 10-13 stop conditi on .......................................................................................................... .....................................248 10-14 wait si gnal ............................................................................................................. .......................................249 10-15 arbitration timing ex ample.............................................................................................. ..............................271 10-16 communication re servation timing ........................................................................................ ......................274 10-17 timing for acknowledging communication re servat ions ..................................................................... .........274 10-18 communication rese rvation flow chart.................................................................................... ....................275 10-19 master operat ion flow chart............................................................................................. ............................277 10-20 slave operat ion flow chart.............................................................................................. .............................278 10-21 example of master to slave communication (when 9-clock wait is selected for both master and sl ave) .................................................................................................................... .................................280
user?s manual u12768ej4v1ud 21 list of figures (4/6) figure no. title page 10-22 example of slave to master communication (when 9-clock wait is selected for both master and sl ave) .................................................................................................................... ................................. 283 10-23 block diagr am of uartn .................................................................................................. ............................ 287 10-24 settings of asimn (operation stop m ode) ................................................................................. ................... 294 10-25 asimn setti ng (uart mode) ............................................................................................... ......................... 295 10-26 asisn setti ng (uart mode) ............................................................................................... .......................... 296 10-27 brgcn setti ng (uart mode)............................................................................................... ........................ 297 10-28 brgmc0 and brgmc 01 settings (u art m ode) ................................................................................. ........ 298 10-29 brgmc1 setti ngs (uar t mode) ............................................................................................. ..................... 299 10-30 error tolerance (when k = 16), including sa mpling e rrors ................................................................ ........... 301 10-31 format of transmit/receive data in asynchronous se rial inte rface ........................................................ ..... 302 10-32 timing of asynchronous serial in terface transmit co mpletion in terr upt ................................................... .... 304 10-33 timing of asynchronous serial in terface receive co mpletion in terr upt .................................................... .... 305 10-34 receive error ti ming.................................................................................................... ................................. 306 11-1 block diagram of a/d c onverter........................................................................................... ......................... 309 11-2 basic operation of a/d c onverter ......................................................................................... ........................ 317 11-3 relationship between analog input voltage and a/d c onversion resu lt...................................................... 318 11-4 a/d conversion by hardware start (with falling edge spec ified) ........................................................... ...... 320 11-5 a/d conversion by softwar e start ......................................................................................... ........................ 321 11-6 handling of analog input pin ............................................................................................. ............................ 323 11-7 a/d conversion end interr upt request gener ation ti ming ................................................................... ........ 324 11-8 handling of av dd pin ........................................................................................................................... .......... 325 11-9 overa ll erro r ............................................................................................................ ...................................... 326 11-10 quantizat ion e rror ...................................................................................................... ................................... 327 11-11 zero-sca le e rror ........................................................................................................ .................................... 327 11-12 full-sc ale e rror ........................................................................................................ ..................................... 328 11-13 differential linearity error............................................................................................ .................................. 328 11-14 integral linearity error ................................................................................................ ................................... 329 11-15 samp ling ti me ........................................................................................................... ................................... 329 12-1 block diagr am of dmac.................................................................................................... ............................ 331 12-2 correspondence between dran setting value and internal ram (4 kb)..................................................... 333 12-3 correspondence between dran setting value and internal ram (8 kb)..................................................... 334 12-4 dma transfer operation timing............................................................................................ ........................ 338 12-5 processing when transfer requests dm a0 to dma2 are g enerated simu ltaneously ................................. 339 13-1 block diagr am of rto..................................................................................................... .............................. 341 13-2 configuration of real-t ime output buffe r regist ers ....................................................................... .............. 342 13-3 example of operation timing of rto (when extr = 0, byte = 0)............................................................. 346
user?s manual u12768ej4v1ud 22 list of figures (5/6) figure no. title page 14-1 block diagram of p00 to p07.............................................................................................. ...........................352 14-2 block diagram of p10, p12, and p1 5 ....................................................................................... .....................356 14-3 block diagram of p11 and p1 4............................................................................................. .........................357 14-4 block diagr am of p13 ..................................................................................................... ...............................358 14-5 block diagram of p20, p23, and p2 5 ....................................................................................... .....................362 14-6 block diagr am of p21 ..................................................................................................... ...............................363 14-7 block diagr am of p22 ..................................................................................................... ...............................364 14-8 block diagr am of p24 ..................................................................................................... ...............................365 14-9 block diagram of p26 and p2 7............................................................................................. .........................366 14-10 block diagram of p30 to p33............................................................................................. ............................369 14-11 block diagram of p34 and p3 5............................................................................................ ..........................370 14-12 block diagram of p36 and p3 7............................................................................................ ..........................371 14-13 block diagram of p 40 to p47 and p 50 to p57 .............................................................................. .................374 14-14 block diagram of p60 to p65............................................................................................. ............................376 14-15 block diagram of p 70 to p77 and p 80 to p83 .............................................................................. .................378 14-16 block diagram of p90 to p95............................................................................................. ............................381 14-17 block diagr am of p96 .................................................................................................... ................................382 14-18 block diagram of p100 to p107........................................................................................... ..........................386 14-19 block diagram of p110 to p113........................................................................................... ..........................389 14-20 block diagr am of p114 ................................................................................................... ...............................389 14-21 block diagr am of p120 ................................................................................................... ...............................392 15-1 system reset ti ming...................................................................................................... ...............................397 16-1 wiring example of v850/sa1 flas h writing adapter (fa100gc- 8eu) ..........................................................4 00 16-2 wiring example of v850/sa1 fl ash writing adapter (fa-121f 1-ea6) .......................................................... 402 16-3 environment for writi ng programs to flash me mory ......................................................................... ............404 16-4 communication with dedicat ed flash progra mmer (uar t0).................................................................... ....404 16-5 communication with dedica ted flash progr ammer (c si0)..................................................................... .......405 16-6 communication with dedicated flash programmer (csi0 + hs)................................................................ ...405 16-7 connection example of v pp pin ..................................................................................................................... 407 16-8 conflict of signals (ser ial interface input pin)......................................................................... .......................408 16-9 malfunction of other device.............................................................................................. .............................408 16-10 conflict of signals (reset pin)......................................................................................... ............................409 16-11 manipulation proc edure of flas h memo ry .................................................................................. ...................410 16-12 flash memory programmi ng m ode........................................................................................... .....................411 16-13 communica tion co mmand ................................................................................................... .........................411 16-14 outline of self-progr ammi ng ............................................................................................ .............................413 16-15 outline of self-p rogramming in terface................................................................................... ........................415 16-16 example of self-progra mming circuit c onfigurat ion....................................................................... ...............416
user?s manual u12768ej4v1ud 23 list of figures (6/6) figure no. title page 16-17 timing to apply voltage to v pp pin ................................................................................................................ 416 16-18 area conf igurat ion...................................................................................................... ................................... 422 16-19 flow of eras ing flash memory ............................................................................................ .......................... 428 16-20 successive writing flow................................................................................................. ............................... 429 16-21 internal verify flow.................................................................................................... .................................... 430 16-22 flow of acquiri ng flash in formati on ..................................................................................... ......................... 431 16-23 functional outline of self-programmi ng libr ary .......................................................................... .................. 432 16-24 outline of self-progra mming library c onfigurat ion ....................................................................... ................ 433 a-1 100-pin plastic lqfp (fine pitch) (14 14) .................................................................................................. 466 a-2 121-pin plastic fbga (fine pitch) (12 12) ................................................................................................. 467
user?s manual u12768ej4v1ud 24 list of tables (1/3) table no. title page 1-1 list of v 850/sa1 pr oducts.................................................................................................. .............................27 2-1 pin i/o buffer power s upplie s .............................................................................................. ...........................38 2-2 operating states of pi ns in each o perating mode ........................................................................... ...............43 3-1 program regist ers......................................................................................................... ..................................61 3-2 system regi ster nu mbers ................................................................................................... ............................62 3-3 interrupt/e xception table................................................................................................. ................................72 4-1 bus c ontrol pins .......................................................................................................... ....................................89 4-2 number of access clocks................................................................................................... .............................90 4-3 bus priori ty .............................................................................................................. ......................................105 5-1 interrupt source list .................................................................................................... .................................107 5-2 interrupt contro l register (xxicn) ........................................................................................ ..........................124 5-3 priorities of in terrupts and e xcepti ons ................................................................................... ........................132 6-1 operating status es in ha lt m ode .......................................................................................... .....................145 6-2 operating status es in id le m ode .......................................................................................... ......................147 6-3 operating statuses in software stop mode.................................................................................. ...............149 7-1 configuration of timers 0 and 1........................................................................................... ..........................155 7-2 valid edge of tin0 pin and capture tri gger of crn0 ........................................................................ ............156 7-3 valid edge of tin1 pin and capture tri gger of crn0 ........................................................................ ............156 7-4 valid edge of tin0 pin and capture tri gger of crn1 ........................................................................ ............157 7-5 configuration of timers 2 to 5............................................................................................ ............................190 8-1 interval time of interval timer ........................................................................................... ............................209 8-2 configuration of watch timer .............................................................................................. ..........................209 8-3 interval time of interval timer ........................................................................................... ............................211 9-1 loop detection time of watc hdog time r ..................................................................................... .................214 9-2 interval time of interval timer ........................................................................................... ............................214 9-3 watchdog timer configur ation .............................................................................................. ........................215 9-4 loop detection time of watc hdog time r ..................................................................................... .................218 9-5 interval time of interval timer ........................................................................................... ............................219 10-1 configurat ion of csin .................................................................................................... ................................222 10-2 configuration of i 2 c.............................................................................................................................. ..........231 10-3 intiicn generation timing and wait control ............................................................................... .................269
user?s manual u12768ej4v1ud 25 list of tables (2/3) table no. title page 10-4 extension c ode bit defi niti ons ........................................................................................... ........................... 270 10-5 status during arbitration and interrupt request g eneration timing........................................................ ...... 272 10-6 wait peri ods ............................................................................................................. ..................................... 273 10-7 configurat ion of uartn ................................................................................................... ............................. 286 10-8 relationship between main clock and baud ra te ............................................................................ ............ 301 10-9 receive error c auses ..................................................................................................... .............................. 306 11-1 configuration of a/d c onverter........................................................................................... ........................... 310 11-2 a/d conversion time sele ction............................................................................................ ......................... 314 13-1 configurat ion of rto..................................................................................................... ................................ 341 13-2 operation when real -time output buffer regi sters are m anipulat ed......................................................... . 342 13-3 operation mode and output tri gger of real-tim e output port ............................................................... ...... 344 14-1 pin i/o buffer power s upplie s ............................................................................................ ........................... 348 14-2 alternate func tions of port 0 ............................................................................................ ............................. 349 14-3 alternate func tions of port 1 ............................................................................................ ............................. 353 14-4 alternate func tions of port 2 ............................................................................................ ............................. 359 14-5 alternate func tions of port 3 ............................................................................................ ............................. 367 14-6 alternate functi ons of port s 4 and 5 ..................................................................................... ........................ 372 14-7 alternate func tions of port 6 ............................................................................................ ............................. 375 14-8 alternate functi ons of port s 7 and 8 ..................................................................................... ........................ 377 14-9 alternate func tions of port 9 ............................................................................................ ............................. 379 14-10 alternate func tions of port 10 .......................................................................................... ............................. 383 14-11 alternate func tions of port 11 .......................................................................................... ............................. 387 14-12 alternate func tion of po rt 12........................................................................................... .............................. 390 14-13 setting when port pin is used for alter nate func tion ................................................................... ............... 393 16-1 wiring table of v850/sa1 flas h writing adapter (fa-100g c-8eu) ............................................................ . 401 16-2 wiring table of v850/sa1 flas h writing adapter (fa-121f 1-ea6)............................................................ ... 403 16-3 signal generation of dedicated fl ash programmer (pg-fp 3 or pg-f p4) .................................................... 406 16-4 pins used by each serial in terface ....................................................................................... ........................ 407 16-5 list of co mmunicati on m odes .............................................................................................. ......................... 411 16-6 commands for flas h memory control........................................................................................ ................... 412 16-7 respons e comm ands ........................................................................................................ ........................... 412 16-8 func tion li st ............................................................................................................ ...................................... 414 16-9 software envir onmental c onditi ons........................................................................................ ....................... 417 16-10 self-programmi ng function numbers ....................................................................................... .................... 418 16-11 calling parame ters ...................................................................................................... .................................. 419 16-12 description of ram para meter ............................................................................................ .......................... 420
user?s manual u12768ej4v1ud 26 list of tables (3/3) table no. title page 16-13 errors during self-progr amming.......................................................................................... ..........................421 16-14 flash informa tion ....................................................................................................... ....................................421 19-1 surface mounting ty pe soldering conditi ons................................................................................ ................462 c-1 symbols in operand descr iption ............................................................................................ .......................473 c-2 symbols us ed for op code ................................................................................................... ..........................474 c-3 symbols used for operation de scripti on .................................................................................... ...................474 c-4 symbols used fo r flag oper ation........................................................................................... .......................475 c-5 condi tion c odes ........................................................................................................... .................................475
user?s manual u12768ej4v1ud 27 chapter 1 introduction the v850/sa1 is a low-power series product in the nec electronics v850 seri es of single-chip microcontrollers designed for real-time control. 1.1 general the v850/sa1 is a 32-bit single-chip microcontroller t hat includes the v850 series cpu core, and peripheral functions such as rom/ram, a timer/counter, a serial interface, an a/d conver ter, and a dma controller. in addition to high real-time response characteristics and 1-clock-pitch basic inst ructions, the v850/sa1 has multiply, saturation operation, and bit m anipulation instructions r ealized with a hardware multiplier for digital servo control. moreover, as a real-time control system, the v850/sa1 enables the realization of extremely high cost- performance for applications that requi re low power consumption, such as camcorders and other av equipment, and portable telephone equipment such as cellular phones and phs phone systems. table 1-1. list of v850/sa1 products rom product name i 2 c function type size ram size package pd703014a not available pd703014ay available 121-pin fbga (12 12) pd703014b not available pd703014by available 64 kb 100-pin lqfp (14 14) pd703015a not available pd703015ay available 121-pin fbga (12 12) pd703015b not available pd703015by available 128 kb 4 kb 100-pin lqfp (14 14) pd703017a not available pd703017ay available mask rom 256 kb 8 kb 100-pin lqfp (14 14)/ 121-pin fbga (12 12) pd70f3015b not available pd70f3015by available 128 kb 4 kb 100-pin lqfp (14 14) pd70f3017a not available pd70f3017ay available flash memory 256 kb 8 kb 100-pin lqfp (14 14)/ 121-pin fbga (12 12)
chapter 1 introduction user?s manual u12768ej4v1ud 28 1.2 features { number of instructions 74 { minimum instruction execution time 50 ns (@20 mhz operation with main clock (f xx )) 58.8 ns (@17 mhz operation with main clock (f xx )) 30.5 s (@32.768 khz operation with subclock (f xt )) { general-purpose registers 32 bits 32 registers { instruction set signed multiplication (16 16 32): 100 ns (@20 mhz operation) (able to execute instructions in paralle l continuously without cr eating any register hazards) saturation operations (overflow and under flow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space 16 mb of linear addr ess space (for programs and data) external expandability: expandable to 4 mb memory block allocation function: 2 mb per block programmable wait function idle state insertion function { external bus interface 16-bit data bus (address/data multiplex) address bus: separate output enabled bus hold function external wait function { internal memory pd703014a, 703014ay, 703014b, 703014by (mask rom: 64 kb/ram: 4 kb) pd703015a, 703015ay, 703015b, 703015by (mask rom: 128 kb/ram: 4 kb) pd703017a, 703017ay (mask rom: 256 kb/ram: 8 kb) pd70f3015b, 70f3015by (flash memory: 128 kb/ram: 4 kb) pd70f3017a, 70f3017ay (flash memory: 256 kb/ram: 8 kb) { interrupts and exceptions external interrupts: 8 sources (5 sources note ) internal interrupts: 24 sources software exceptions: 32 sources exception trap: 1 source interrupt priorities can be changed (8 levels) note number of external interrupts t hat can release software stop mode. { i/o lines total: 85 (13 input ports and 72 i/o ports) { timer/counter 16-bit timer: 2 channels (pwm output) 8-bit timer: 4 channels (pwm outputs, cascade connection enabled) { watch timer when operating under subclock or main clock: 1 channel { watchdog timer 1 channel
chapter 1 introduction user?s manual u12768ej4v1ud 29 { serial interface (sio) asynch ronous serial interface (uart) clocked serial interface (csi) i 2 c bus interface (i 2 c) ( pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only) uart: 1 channel csi: 1 channel uart/csi: 1 channel i 2 c/csi: 1 channel uart dedicated baud rate generator: 2 channels { a/d converter 10-bit resolution: 12 channels { dma controller internal ram on-chip peripheral i/o: 3 channels { real-time output port 8 bits 1 channel or 4 bits 2 channels { clock generator during main clock or subclock operation 5-level cpu clock (including clock-through and sub operations) { power-saving functions halt/idle/software stop modes { package 100-pin plastic lqfp (fine pitch, 14 14) 121-pin plastic fbga (12 12) { cmos structure fully static circuits
chapter 1 introduction user?s manual u12768ej4v1ud 30 1.3 applications general battery-driven equipment such as camcorders (including dvc), meters, etc. 1.4 ordering information part number package internal rom pd703014af1- -ea6 121-pin plastic fbga (1212) 64 kb (mask rom) pd703014af1- -ea6-a 121-pin plastic fbga (1212) 64 kb (mask rom) pd703014ayf1- -ea6 121-pin plastic fbga (1212) 64 kb (mask rom) pd703014ayf1- -ea6-a 121-pin plastic fbga (1212) 64 kb (mask rom) pd703014bf1- -ea6-a 121-pin plastic fbga (1212) 64 kb (mask rom) pd703014bgc- -8eu 100-pin plastic lqfp (fine pitch) (1414) 64 kb (mask rom) pd703014bgc- -8eu-a 100-pin plastic lqfp (fine pitch) (1414) 64 kb (mask rom) pd703014byf1- -ea6-a 121-pin plastic fbga (1212) 64 kb (mask rom) pd703014bygc- -8eu 100-pin plastic lqfp (fine pitch) (1414) 64 kb (mask rom) pd703014bygc- -8eu-a 100-pin plastic lqfp (fine pitch) (1414) 64 kb (mask rom) pd703015af1- -ea6 121-pin plastic fbga (1212) 128 kb (mask rom) pd703015af1- -ea6-a 121-pin plastic fbga (1212) 128 kb (mask rom) pd703015ayf1- -ea6 121-pin plastic fbga (1212) 128 kb (mask rom) pd703015ayf1- -ea6-a 121-pin plastic fbga (1212) 128 kb (mask rom) pd703015bf1- -ea6-a 121-pin plastic fbga (1212) 128 kb (mask rom) pd703015bgc- -8eu 100-pin plastic lqfp (fine pitch) (1414) 128 kb (mask rom) pd703015bgc- -8eu-a 100-pin plastic lqfp (fine pitch) (1414) 128 kb (mask rom) pd703015byf1- -ea6-a 121-pin plastic fbga (1212) 128 kb (mask rom) pd703015bygc- -8eu 100-pin plastic lqfp (fine pitch) (1414) 128 kb (mask rom) pd703015bygc- -8eu-a 100-pin plastic lqfp (fine pitch) (1414) 128 kb (mask rom) pd703017af1- -ea6 121-pin plastic fbga (1212) 256 kb (mask rom) pd703017af1- -ea6-a 121-pin plastic fbga (1212) 256 kb (mask rom) pd703017agc- -8eu 100-pin plastic lqfp (fine pitch) (1414) 256 kb (mask rom) pd703017agc- -8eu-a 100-pin plastic lqfp (fine pitch) (1414) 256 kb (mask rom) pd703017ayf1- -ea6 121-pin plastic fbga (1212) 256 kb (mask rom) pd703017ayf1- -ea6-a 121-pin plastic fbga (1212) 256 kb (mask rom) pd703017aygc- -8eu 100-pin plastic lqfp (fine pitch) (1414) 256 kb (mask rom) pd703017aygc- -8eu-a 100-pin plastic lqfp (fine pitch) (1414) 256 kb (mask rom) pd70f3015bf1-ea6-a 121-pin plastic fbga (1212) 128 kb (flash memory) pd70f3015bgc-8eu 100-pin plastic lqfp (fine pitch) (1414) 128 kb (flash memory) pd70f3015bgc-8eu-a 100-pin plastic lqfp (fine pitch) (1414) 128 kb (flash memory) pd70f3015byf1-ea6-a 121-pin plastic fbga (1212) 128 kb (flash memory) pd70f3015bygc-8eu 100-pin plastic lqfp (fine pitch) (1414) 128 kb (flash memory) pd70f3015bygc-8eu-a 100-pin plastic lqfp (fine pitch) (1414) 128 kb (flash memory) pd70f3017af1-ea6 121-pin plastic fbga (1212) 256 kb (flash memory) pd70f3017af1-ea6-a 121-pin plastic fbga (1212) 256 kb (flash memory) pd70f3017agc-8eu 100-pin plastic lqfp (fine pitch) (1414) 256 kb (flash memory) pd70f3017agc-8eu-a 100-pin plastic lqfp (fine pitch) (1414) 256 kb (flash memory) pd70f3017ayf1-ea6 121-pin plastic fbga (1212) 256 kb (flash memory) pd70f3017ayf1-ea6-a 121-pin plastic fbga (1212) 256 kb (flash memory) pd70f3017aygc-8eu 100-pin plastic lqfp (fine pitch) (1414) 256 kb (flash memory) pd70f3017aygc-8eu-a 100-pin plastic lqfp (fine pitch) (1414) 256 kb (flash memory) remarks 1. ? ? indicates rom code suffix. 2. the v850/sa1 does not include any romless versions. 3. products with -a at the end of t he part number are lead-free products.
chapter 1 introduction user?s manual u12768ej4v1ud 31 1.5 pin configuration 100-pin plastic lqfp (fine pitch) (14 14) ? pd703014bgc- -8eu ? pd703017agc- -8eu ? pd70f3017agc-8eu ? pd703014bgc- -8eu-a ? pd703017agc- -8eu-a ? pd70f3017agc-8eu-a ? pd703014bygc- -8eu ? pd703017aygc- -8eu ? pd70f3017aygc-8eu ? pd703014bygc- -8eu-a ? pd703017aygc- -8eu-a ? pd70f3017aygc-8eu-a ? pd703015bgc- -8eu ? pd70f3015bgc-8eu ? pd703015bgc- -8eu-a ? pd70f3015bgc-8eu-a ? pd703015bygc- -8eu ? pd70f3015bygc-8eu ? pd703015bygc- -8eu-a ? pd70f3015bygc-8eu-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p20/si2 p15/sck1/asck0 p14/so1/txd0 p13/si1/rxd0 p12/sck0/scl note 2 p11/so0 p10/si0/sda note 2 p07/intp6 p06/intp5/rtptrg p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p107/rtp7/a12 p110/a1 p111/a2 p112/a3 p113/a4 reset p114/xt1 xt2 v dd x2 x1 v ss clkout p120/wait p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak p96/hldrq p40/ad0 p41/ad1 p42/ad2 p43/ad3 p21/so2 p22/sck2 p23/rxd1 p24/txd1 p25/asck1 v dd v ss p26/ti2/to2 p27/ti3/to3 p30/ti00 p31/ti01 p32/ti10 p33/ti11 p34/to0/a13 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 ic/v pp note 1 p100/rtp0/a5 p101/rtp1/a6 p102/rtp2/a7 p103/rtp3/a8 p104/rtp4/a9 p105/rtp5/a10 p106/rtp6/a11 p71/ani1 p70/ani0 av ref av ss av dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 notes 1. pd703014b, 703014by, 703015b, 703015by, 703017a, 703017ay: ic (connect directly to v ss ) pd70f3015b, 70f3015by, 70f3017a, 70f3017ay: v pp (connect to v ss in normal operation mode) 2. scl and sda are available only in the pd703014by, 703015by, 703017ay, 70f3015by, and 70f3017ay.
chapter 1 introduction user?s manual u12768ej4v1ud 32 121-pin plastic fbga (12 12) ? pd703014af1- -ea6 ? pd703015ayf1- -ea6 ? pd70f3015bf1-ea6-a ? pd703014af1- -ea6-a ? pd703015ayf1- -ea6-a ? pd70f3015byf1-ea6-a ? pd703014ayf1- -ea6 ? pd703015bf1- -ea6-a ? pd70f3017af1-ea6 ? pd703014ayf1- -ea6-a ? pd703015byf1- -ea6-a ? pd70f3017af1-ea6-a ? pd703014bf1- -ea6-a ? pd703017af1- -ea6 ? pd70f3017ayf1-ea6 ? pd703014byf1- -ea6-a ? pd703017af1- -ea6-a ? pd70f3017ayf1-ea6-a ? pd703015af1- -ea6 ? pd703017ayf1- -ea6 ? pd703015af1- -ea6-a ? pd703017ayf1- -ea6-a top view bottom view nmlkjhgfedcba abcdefghjklmn 13 12 11 10 9 8 7 6 5 4 3 2 1 pin no. name pin no. name pin no. name pin no. name pin no. name pin no. name a1 p20 b8 p83 d2 v dd g11 p60 k13 bv dd m7 v ss a2 p15 b9 p80 d3 v ss g12 p56 l1 p104 m8 v ss a3 v ss b10 p75 d11 av dd g13 p57 l2 p105 m9 p92 a4 p13 b11 av ss d12 av dd h1 p34 l3 reset m10 p95 a5 p11 b12 av ss d13 av dd h2 p37 l4 v dd m11 p41 a6 p06 b13 p71 e1 p25 h3 p35 l5 v ss m12 p45 a7 p03 c1 p22 e2 v dd h11 p55 l6 x2 m13 p44 a8 p00 c2 p23 e3 p30 h12 p53 l7 p90 n1 p107 a9 p81 c3 v ss e11 av dd h13 p54 l8 p120 n2 p110 a10 p76 c4 p24 e12 p64 j1 ic/v pp note l9 p93 n3 p112 a11 p73 c5 p07 e13 p65 j2 ic/v pp note l10 p96 n4 v dd a12 p72 c6 p04 f1 p26 j3 p100 l11 bv ss n5 xt1 a13 av ss c7 p01 f2 p27 j11 p52 l12 bv ss n6 v ss b1 p21 c8 p82 f3 p33 j12 p50 l13 bv ss n7 v ss b2 p14 c9 p77 f11 p63 j13 p51 m1 p106 n8 clkout b3 v ss c10 p74 f12 p61 k1 p101 m2 p111 n9 p91 b4 p12 c11 av ss f13 p62 k2 p102 m3 p113 n10 p94 b5 p10 c12 p70 g1 p31 k3 p103 m4 v dd n11 p40 b6 p05 c13 av ref g2 p32 k11 p46 m5 xt2 n12 p42 b7 p02 d1 v dd g3 p36 k12 p47 m6 x1 n13 p43 note pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, pd703017a, 703017ay: ic (connect directly to v ss ) pd70f3015b, 70f315by, 70f3017a, 70f3017ay: v pp (connect to v ss in normal operation mode) remarks 1. alternate pin names are omitt ed. alternate pins are identic al to the 100-pin plastic lqfp. however, scl and sda are available only in the pd703014ay, 703014by, 703015ay, 703015by, 70f3015by, 703017ay, and 70f3017ay. 2. connect the d4 pin directly to v ss .
chapter 1 introduction user?s manual u12768ej4v1ud 33 pin identification a1 to a21: address bus p90 to p96: port 9 ad0 to ad15: address/data bus p100 to p107: port 10 adtrg: a/d trigger input p110 to p114: port 11 ani0 to ani11: analog input p120 port 12 asck0, asck1: asynchronous serial clock rd: read strobe astb: address strobe reset: reset av dd : power supply for analog rtp0 to rtp7: real-time output port av ref : analog reference voltage rtptrg: rtp trigger av ss : ground for analog r/w: read/write status bv dd : power supply for bus interface rxd0, rxd1: receive data bv ss : ground for bus interface sck0 to sck2: serial clock clkout: clock output scl: serial clock dstb: data strobe sda: serial data hldak: hold acknowledge si0 to si2: serial input hldrq: hold request so0 to so2: serial output ic: internally connected ti00, ti01, ti10, intp0 to intp6: interrupt request from per ipherals ti11, ti2 to ti5: timer input lben: lower byte enable to0 to to5: timer output nmi: non-maskable interrupt request txd0, txd1: transmit data p00 to p07: port 0 uben: upper byte enable p10 to p15: port 1 v dd : power supply p20 to p27: port 2 v pp : programming power supply p30 to p37: port 3 v ss : ground p40 to p47: port 4 wait: wait p50 to p57: port 5 wrh: write strobe high level data p60 to p65: port 6 wrl: write strobe low level data p70 to p77: port 7 x1, x2 : crystal for main clock p80 to p83: port 8 xt1, xt2: crystal for subclock
chapter 1 introduction user?s manual u12768ej4v1ud 34 1.6 function blocks 1.6.1 internal block diagram nmi ti00, ti01, ti10, ti11 to0, to1 sio ti2/to2 ti3/to3 ti4/to4 ti5/to5 so0 si0/sda note 3 sck0/scl note 3 intp0 to intp6 intc timer/counter 16-bit timer: tm0, tm1 8-bit timer: tm2 to tm5 so1/txd0 si1/rxd0 sck1/asck0 csi1/uart0 csi0/i 2 c note 4 so2 si2 sck2 csi2 txd1 rxd1 asck1 uart1 dmac: 3 ch watch timer watchdog timer rom note 1 ram note 2 pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel register cpu hldrq (p96) hldak (p95) astb (p94) dstb/rd (p93) r/w/wrh (p92) uben (p91) lben/wrl (p90) wait a1 to a12 a13 to a15 (p34 to p36) a16 to a21 (p60 to p65) ad0 to ad15 ports rtp cg a/d converter (p40 to p47, p50 to p57) (p100 to p107, p110 to p113) p120 p114 p110 to p113 p100 to p107 p90 to p96 p80 to p83 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p15 p00 to p07 rtp0 to rtp7 rtptrg av dd av ref av ss ani0 to ani11 adtrg clkout x1 x2 xt1 (p114) xt2 reset v dd v ss bv dd bv ss v pp note 5 ic note 6 instruction queue bcu notes 1. pd703014a, 703014ay, 703014b, 703014by: 64 kb (mask rom) pd703015a, 703015ay, 703015b, 703015by: 128 kb (mask rom) pd703017a, 703017ay: 256 kb (mask rom) pd70f3015b, 70f3015by: 128 kb (flash memory) pd70f3017a, 70f3017ay: 256 kb (flash memory) 2. pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 70f3015b, 70f3015by: 4 kb pd703017a, 703017ay, 70f3017a, 70f3017ay: 8 kb 3. the scl and sda pins are available only in the pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f 3015by, and 70f3017ay. 4. the i 2 c function is available only in the pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay. 5. pd70f3015b, 70f3015by, 70f3017a and 70f3017ay 6. pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 703017a, and 703017ay
chapter 1 introduction user?s manual u12768ej4v1ud 35 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline contro l to enable single-clock execution of addr ess calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, su ch as the multiplier (16 bits 16 bits 32 bits) and the 32-bit barrel shifter help accelerate processing of complex instructions. (2) bus control unit (bcu) the bcu starts a required exter nal bus cycle based on the physical addr ess obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instru ction code is stored in an instruction queue. (3) rom this consists of a mask rom or flash memo ry mapped to the address space starting at 00000000h. rom can be accessed by the cpu in one clock cycle during instruction fetch. the internal rom capacity and internal rom area vary as follows according to the product. product name internal rom capacity internal rom area pd703014a, 703014ay, 703014b, 703014by 64 kb (mask rom) xx000000h to xx00ffffh pd703015a, 703015ay, 703015b, 703015by 128 kb (mask rom) pd70f3015b, 70f3015by 128 kb (flash memory) xx000000h to xx01ffffh pd703017a, 703017ay 256 kb (mask rom) pd70f3017a, 70f3017ay 256 kb (flash memory) xx000000h to xx03ffffh (4) ram the internal ram capacity and internal ram area vary as follows according to the product. ram can be accessed by the cpu in one clock cycle during data access. product name internal ram capacity internal ram area pd703014a, 703014ay, 703015b, 703015by pd703015a, 703015ay, 703015b, 703015by xxffe000h to xxffefffh pd70f3015b, 703015by 4 kb pd703017a, 703017ay pd70f3017a, 70f3017ay 8 kb xxffd000h to xxffefffh (5) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified fo r these interrupt requests, and multiple servicing control can be perfo rmed for interrupt sources.
chapter 1 introduction user?s manual u12768ej4v1ud 36 (6) clock generator (cg) the clock generator includes two types of oscillators: one each for the main clock (f xx ) and subclock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (7) timer/counter a two-channel 16-bit timer/event c ounter and a four-channel 8-bit timer/ event counter are equipped, enabling measurement of pulse intervals and frequen cy as well as programmable pulse output. the two-channel 8-bit timer/event c ounter can be connected via a cascade connection to enable use as a 16-bit timer. (8) watch timer this timer generates an interrupt of the reference time period (0.5 seconds) for counting the clock (the 32.768 khz subclock or the 16.777 mhz main clock). at the same ti me, the watch timer can be used as an interval timer for the main clock. (9) watchdog timer a watchdog timer is equipped to detect program loops, system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-mask able interrupt request (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs. (10) serial interface (sio) the v850/sa1 includes four serial in terface channels: for the asynchronous serial interface (uart0, uart1), clocked serial interface (csi0 to csi2), and i 2 c bus interface. one of thes e channels is switchable between the uart and csi and another is switchable between csi and i 2 c. two channels are fixed to uart and csi, respectively. for uart 0 and uart1, data is transferred via the txd0, txd1, rxd0, and rxd1 pins. for csi0 to csi2, data is transferred via the so0 to so2, si0 to si2, and sck0 to sck2 pins. for i 2 c, data is transferred via the sda and scl pins. i 2 c is equipped only in the pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay. uart also has a two-channel dedicated baud rate generator. (11) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion uses the successive approximation method. (12) dma controller a three-channel dma controller is equipped. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to interr upt requests sent by on-chip peripheral i/o. (13) real-time output port (rtp) the rtp is a real-time output function that transfers previously set 8-bit data to an output latch when an external trigger signal or timer compare register match signal occurs. it can also be used in a 4-bit 2-channel configuration.
chapter 1 introduction user?s manual u12768ej4v1ud 37 (14) ports as shown below, the following ports have general- purpose port functions and control pin functions. port i/o port function control function port 0 8-bit i/o general- purpose port nmi, external interrupt, a/d c onverter trigger, rtp trigger port 1 6-bit i/o serial interface port 2 8-bit i/o serial interface, timer i/o port 3 8-bit i/o timer i/o, external address bus port 4 8-bit i/o external address/data bus port 5 port 6 6-bit i/o external address bus port 7 8-bit input a/d converter analog input port 8 4-bit input port 9 7-bit i/o external bus interface control signal i/o port 10 8-bit i/o real-time output port, external address bus port 11 4-bit i/o, 1-bit input external address bus, subclock input port 12 1-bit i/o wait control
user?s manual u12768ej4v1ud 38 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins of the v850/sa1 are described below di vided into port pins and non-port pins. there are three types of power supplies for the pin i/o buffers: av dd , bv dd , and v dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies power supply corresponding pins usable voltage range av dd port 7, port 8 2.7 v av dd 3.6 v bv dd port 4, port 5, port 6, port 9, port 12, clkout 2.7 v bv dd 3.6 v v dd port 0, port 1, port 2, port 3, port 10, port 11, reset 2.7 v v dd 3.6 v (1) port pins (1/3) pin name i/o pull function alternate function p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5/rtptrg p07 i/o yes port 0 8-bit i/o port input/output mode can be specified in 1-bit units. intp6 p10 si0/sda note p11 so0 p12 sck0/scl note p13 si1/rxd0 p14 so1/txd0 p15 i/o yes port 1 6-bit i/o port input/output mode can be specified in 1-bit units. sck1/asck0 p20 si2 p21 so2 p22 sck2 p23 rxd1 p24 txd1 p25 asck1 p26 ti2/to2 p27 i/o yes port 2 8-bit i/o port input/output mode can be specified in 1-bit units. ti3/to3 note pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u12768ej4v1ud 39 (2/3) pin name i/o pull function alternate function p30 ti00 p31 ti01 p32 ti10 p33 ti11 p34 to0/a13 p35 to1/a14 p36 ti4/to4/a15 p37 i/o yes port 3 8-bit i/o port input/output mode can be specified in 1-bit units. ti5/to5 p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 i/o no port 4 8-bit i/o port input/output mode can be specified in 1-bit units. ad7 p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 i/o no port 5 8-bit i/o port input/output mode can be specified in 1-bit units. ad15 p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 p65 i/o no port 6 6-bit i/o port input/output mode can be specified in 1-bit units. a21 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u12768ej4v1ud 40 (3/3) pin name i/o pull function alternate function p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 input no port 7 8-bit input port ani7 p80 ani8 p81 ani9 p82 ani10 p83 input no port 8 4-bit input port ani11 p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output mode can be specified in 1-bit units. hldrq p100 rtp0/a5 p101 rtp1/a6 p102 rtp2/a7 p103 rtp3/a8 p104 rtp4/a9 p105 rtp5/a10 p106 rtp6/a11 p107 i/o yes port 10 8-bit i/o port input/output mode can be specified in 1-bit units. rtp7/a12 p110 a1 p111 a2 p112 a3 p113 i/o yes a4 p114 input no port 11 5-bit i/o port input/output mode can be specified in 1-bit units. p114 is fixed to input mode. xt1 p120 i/o no port 12 1-bit i/o port wait remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u12768ej4v1ud 41 (2) non-port pins (1/2) pin name i/o pull function alternate function a1 to a4 p110 to p113 a5 to a12 p100/rtp0 to p107/rtp7 a13 p34/to0 a14 p35/to1 a15 output yes lower address bus used for external memory expansion p36/ti4/to4 a16 to a21 output no higher address bus used for external memory expansion p60 to p65 ad0 to ad7 p40 to p47 ad8 to ad15 i/o no 16-bit multiplexed addre ss/data bus used for external memory expansion p50 to p57 adtrg input yes a/d converter ex ternal trigger input p05/intp4 ani0 to ani7 input no p70 to p77 ani8 to ani11 input no analog input to a/d converter p80 to p83 asck0 p15/sck1 asck1 input yes serial baud rate cl ock input for uart0 and uart1 p25 astb output no external address strobe signal output p94 av dd ? ? positive power supply for a/d converter ? av ref input ? reference voltage input for a/d converter ? av ss ? ? ground potential for a/d converter ? bv dd ? ? positive power supply for bus interface ? bv ss ? ? ground potential for bus interface ? clkout output ? internal system clock output ? dstb output no external data strobe signal output p93/rd hldak output no bus hold acknowledge output p95 hldrq input no bus hold request input p96 intp0 to intp3 external interrupt request i nput (analog noise elimination) p01 to p04 intp4 p05/adtrg intp5 p06/rtptrg intp6 input yes external interrupt request input (digital noise elimination) p07 lben output no external data bus?s lower byte enable signal output p90/wrl nmi input yes non-maskable interrupt request input (analog noise elimination) p00 rd output no read strobe signal output p93/dstb reset input ? system reset input ? rtp0 to rtp7 output yes real-time output port p100/a5 to p107/a12 rtptrg input yes rtp exter nal trigger input p06/intp5 r/w output no external read/write status output p92/wrh rxd0 p13/si1 rxd1 input yes serial receive data input for uart0 and uart1 p23 sck0 i/o yes serial clock i/o (3-wir e type) for csi0 to csi2 p12/scl note note pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u12768ej4v1ud 42 (2/2) pin name i/o pull function alternate function sck1 p15/asck0 sck2 i/o yes serial clock i/o (3-w ire type) for csi0 to csi2 p22 scl note 1 i/o yes serial clock i/o for i 2 c p12/sck0 sda note 1 i/o yes serial transmit/receive data i/o for i 2 c p10/si0 si0 p10/sda note 1 si1 p13/rxd0 si2 input yes serial receive data input (3-wire type) for csi0 to csi2 p20 so0 p11 so1 p14/txd0 so2 output yes serial transmit data output (3-wire type) for csi0 to csi2 p21 ti00 external count clock input for tm 0/external capture trigger input p30 ti01 external capture trigger input for tm0 p31 ti10 external count clock input for tm 1/external capture trigger input p32 ti11 external capture trigger input for tm1 p33 ti2 external count clo ck input for tm2 p26/to2 ti3 external count clo ck input for tm3 p27/to3 ti4 external count clock input for tm4 p36/to4/a15 ti5 input yes external count clock input for tm5 p37/to5 to0, to1 pulse signal output for tm0, tm1 p34/a13, p35/a14 to2 pulse signal output for tm2 p26/ti2 to3 pulse signal output for tm3 p27/ti3 to4 pulse signal output for tm4 p36/ti4/a15 to5 output yes pulse signal output for tm5 p37/ti5 txd0 p14/so1 txd1 output yes serial transmit data output for uart0 and uart1 p24 uben output no higher byte enable signal output for external data bus p91 v dd ? ? positive power supply pin ? v pp note 2 ? ? high-voltage application pin for program write/verify ? v ss ? ? ground potential ? wait input yes control signal input for inserting wait in bus cycle p120 wrh higher byte write strobe signal out put for external data bus p92/r/w wrl output no lower byte write strobe signal output for external data bus p90/lben x1 input ? x2 ? no resonator connection for main clock ? xt1 input p114 xt2 ? no resonator connection for subclock ? ic note 3 ? ? internally connected ? notes 1. pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only 2. pd70f3015b, 70f3015by, 70f3017a, and 70f3017ay only 3. pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 703017a, and 703017ay only remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u12768ej4v1ud 43 2.2 pin states the operating states of various pins are described below with refe rence to their operating modes. table 2-2. operating states of pins in each operating mode operating state pin reset note 1 halt mode/ idle state idle mode/ software stop mode bus hold bus cycle inactive note 2 ad0 to ad15 hi-z hi-z hi-z hi-z hi-z a1 to a15 hi-z held held held held note 3 a16 to a21 hi-z held hi-z hi-z held note 3 lben, uben hi-z held hi-z hi-z held note 3 r/w hi-z h hi-z hi-z h dstb, wrl, wrh, rd hi-z h hi-z hi-z h astb hi-z h hi-z hi-z h hldrq ? operating ? operating operating hldak hi-z operating hi-z l operating wait ? ? ? ? ? clkout hi-z operating note 4 l operating note 4 operating note 4 notes 1. pins (except the clkout pin) are used as port pins (input mode) after reset. 2. the bus cycle inactivation timing occurs when the inte rnal memory area is s pecified by the program counter (pc) in the ex ternal expansion mode. 3. ? when the external memory area has not been a ccessed even once after reset is released and the external expansion mode is set: undefined ? when the bus cycle is inactivated after access to the external memory area, or when the external memory area has not been accessed even once afte r the external expansion mode is released and set again: the state of the exter nal bus cycle when the external memory area accessed last is held. 4. low level (l) when in clock output inhibit mode remark hi-z: high impedance held: state is held during previously set external bus cycle l: low-level output h: high-level output ? : input without sampling sa mpled (not acknowledged)
chapter 2 pin functions user?s manual u12768ej4v1ud 44 2.3 description of pin functions (1) p00 to p07 (port 0) 3-state i/o p00 to p07 constitute an 8-bit i/o port that can be set to input or output in 1-bit units. p00 to p07 can also function as an nmi input, external interrupt request inputs, exte rnal trigger for the a/d converter, and external trigger for t he real-time output port. the valid edges of the nmi and intp0 to intp6 pins are specified by the eg p0 and egn0 registers. (a) port function p00 to p07 can be set to input or output in 1- bit units using the port 0 mode register (pm0). (b) alternate functions (i) nmi (non-maskable interrupt request) input this is a non-maskable interrupt request signal input pin. (ii) intp0 to intp6 (interrupt request from peri pherals) input these are external interrupt request input pins. (iii) adtrg (ad trigger input) input this is the a/d converter?s external trigger input pin. this pin is controlled by the a/d converter mode register (adm). (iv) rtptrg (real-time output port trigger input) input this is the real-time output port?s exte rnal trigger input pin. this pin is controlled by t he real-time output port control register (rtpc).
chapter 2 pin functions user?s manual u12768ej4v1ud 45 (2) p10 to p15 (port 1) 3-state i/o p10 to p15 constitute a 6-bit i/o port that can be set to input or output in 1-bit units. p10 to p15 can also function as input or output pins for the serial interface. p10 to p12, p14, and p15 can be selected as normal output or n-ch open-drain output. (a) port function p10 to p15 can be set to input or output in 1- bit units using the port 1 mode register (pm1). (b) alternate functions (i) si0, si1 (serial input 0, 1) input these are the serial receive dat a input pins of csi0 and csi1. (ii) so0, so1 (serial output 0, 1) output these are the serial transmit dat a output pins of csi0 and csi1. (iii) sck0, sck1 (serial clock 0, 1) 3-state i/o these are the serial clock i/o pins for csi0 and csi1. (iv) sda (serial data) i/o this is the serial transmit/receive data i/o pin for i 2 c ( pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only). (v) scl (serial clock) i/o this is the serial clock i/o pin for i 2 c ( pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only). (vi) rxd0 (receive data 0) input this is the serial receive data input pin of uart0. (vii) txd0 (transmit data 0) output this is the serial transmit data output pin of uart0. (viii) asck0 (asynchr onous serial clock 0) input this is the serial baud rate clock input pin of uart0.
chapter 2 pin functions user?s manual u12768ej4v1ud 46 (3) p20 to p27 (port 2) 3-state i/o p20 to p27 constitute an 8-bit i/o port that can be set to input or output in 1-bit units. p20 to p27 can also function as input or output pins for the serial interf ace, and input or out put pins for the timer/counter. p21 and p22 can be selected as norma l output or n-ch open-drain output. (a) port function p20 to p27 can be set to input or output in 1- bit units using the port 2 mode register (pm2). (b) alternate functions (i) si2 (serial input 2) input this is the serial receive data input pin of csi2. (ii) so2 (serial output 2) output this is the serial transmit data output pin of csi2. (iii) sck2 (serial clock 2) 3-state i/o this is the serial clock i/o pin of csi2. (iv) rxd1 (receive data 1) ... input this is the serial receiv e data input pin of uart1. (v) txd1 (transmit data 1) ... output this is the serial transmi t data output pin of uart1. (vi) asck1 (asynchronous serial clock 1) ... input this is the serial baud rate clock input pin of uart1. (vii) ti2 and ti3 (timer input 2, 3) ... input these are the external count clock input pins for timer 2 and timer 3. (viii) to2 and to3 (timer output 2, 3) ... output these are the pulse signal output pins for timer 2 and timer 3.
chapter 2 pin functions user?s manual u12768ej4v1ud 47 (4) p30 to p37 (port 3) 3-state i/o p30 to p37 constitute an 8-bit i/o port that can be set to input or output in 1-bit units. p30 to p37 can also function as input or output pins for the timer/count er, and an address bus (a13 to a15) when memory is expanded externally. (a) port function p30 to p37 can be set to input or output in 1- bit units using the port 3 mode register (pm3). (b) alternate functions (i) ti00, ti01, ti10, ti11, ti4, ti5 (tim er input 00, 01, 10, 11, 4, 5) input these are the external count clock input pins of timer 0, timer 1, timer 4, and timer 5. (ii) to0, to1, to4, to5 (timer output 0, 1, 4, 5) output these are the pulse signal out put pins of timer 0, timer 1, timer 4, and timer 5. (iii) a13 to a15 (address 13 to 15) output these comprise an address bus that is used for exter nal access. these pins operate as the a13 to a15 bit address output pins within a 22-bit address. t he output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing se ts the bus cycle to inactive, the previous bus cycle?s address is retained.
chapter 2 pin functions user?s manual u12768ej4v1ud 48 (5) p40 to p47 (port 4) 3-state i/o p40 to p47 constitute an 8-bit i/o port that can be set to input or output pins in 1-bit units. p40 to p47 can also function as a time division address/data bus (ad0 to ad7) when memory is expanded externally. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as a reference. (a) port function p40 to p47 can be set to input or output in 1- bit units using the port 4 mode register (pm4). (b) alternate functions (external expansion function) p40 to p47 can be set as ad0 to ad7 usi ng the memory expansion mode register (mm). (i) ad0 to ad7 (address/data 0 to 7) 3-state i/o these comprise a multiplexed addre ss/data bus that is used for exter nal access. at the address timing (t1 state), these pins oper ate as ad0 to ad7 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as the lower 8-bit i/o bus pins fo r 16-bit data. the output changes in synchronization with the rising edge of the clock in each state within the bus cycle. when the timing sets the bus cycle to inactive, these pins go into a high-impedance state. (6) p50 to p57 (port 5) 3-state i/o p50 to p57 constitute an 8-bit i/o port that can be set to input or output in 1-bit units. p50 to p57 can also function as i/o port pins and as a time division address/data buses (ad8 to ad15) when memory is expanded externally. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as reference. (a) port function p50 to p57 can be set to input or output in 1- bit units using the port 5 mode register (pm5). (b) alternate functions (external expansion function) p50 to p57 can be set as ad8 to ad15 usi ng the memory expansion mode register (mm). (i) ad8 to ad15 (address/data 8 to 15) 3-state i/o these comprise a multiplexed addre ss/data bus that is used for exter nal access. at the address timing (t1 state), these pins oper ate as ad8 to ad15 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as the higher 8-bit i/o bus pins fo r 16-bit data. the output changes in synchronization with the rising edge of the clock in each state within the bus cycle. when the timing sets the bus cycle to inactive, these pins go into a high-impedance state.
chapter 2 pin functions user?s manual u12768ej4v1ud 49 (7) p60 to p65 (port 6) 3-state i/o p60 to p65 constitute a 6-bit i/o port that can be set to input or output in 1-bit units. p60 to p65 can also function as an address bus (a16 to a21) when memory is expanded externally. when the port 6 is accessed in 8-bit units, the higher 2 bits of port 6 are ignored when they ar e written to and 00 is read when they are read. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as reference. (a) port function p60 to p65 can be set to input or output in 1- bit units using the port 6 mode register (pm6). (b) alternate functions (external expansion function) p60 to p65 can be set as a16 to a21 usi ng the memory expansion mode register (mm). (i) a16 to a21 (address 16 to 21) output these comprise an address bus that is used for exter nal access. these pins operate as the higher 6-bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of t he bus cycle. when the timing sets the bus cycle to inactive, the previous bus cycle?s address is retained. (8) p70 to p77 (port 7), p80 to p83 (port 8) input p70 to p77 constitute an 8-bit input-only port in which all t he pins are fixed to input mode. p80 to p83 constitute a 4-bit input-only port in which all the pins are fixed to input. p70 to p77 and p80 to p83 can also function as analog input pins for the a/d converter. (a) port function p70 to p77 and p80 to p83 are input-only pins. (b) alternate functions p70 to p77 also function as ani0 to ani7 and p80 to p 83 also function as ani8 to ani11, but these alternate functions are not switchable. (i) ani0 to ani11 (analog input 0 to 11) input these are analog input pins for the a/d converter. connect a capacitor bet ween these pins and av ss to prevent noise-related operation faults. also, do not apply voltage that is outside the range for av ss and av ref to pins that are being used as inputs for the a/d converter. if it is possible for noise above the av ref range or below the av ss to enter, clamp these pins using a diode that has a small v f value.
chapter 2 pin functions user?s manual u12768ej4v1ud 50 (9) p90 to p96 (port 9) 3-state i/o p90 to p96 constitute a 7-bit i/o port that can be set to input or output pins in 1-bit units. p90 to p96 can also function as cont rol signal output pins and bus hold contro l signal output pins when memory is expanded externally. during 8-bit access of port 9, the highest bit is ignored during a write operation and is read as a ?0? during a read operation. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as a reference. (a) port function p90 to p96 can be set to input or output in 1- bit units using the port 9 mode register (pm9). (b) alternate functions (external expansion function) p90 to p96 can be set to operate as control signal out puts for external memory expansion using the memory expansion mode register (mm). (i) lben (lower byte enable) output this is a lower byte enable signal output pin for the external 16-bit data bus. during byte access of odd- numbered addresses, these pins are set as inactive (high level). the output changes in synchronization with the rising edge of the clock in t he t1 state of the bus cycle. w hen the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. (ii) uben (upper byte enable) output this is an upper byte enable signal output pin for the external 16-bit data bus. during byte access of even-numbered addresses, these pins are set as inactive (high level). the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. access uben lben a0 word access 0 0 0 halfword access 0 0 0 byte access even-numbered address 1 0 0 odd-numbered address 0 1 1 (iii) r/w (read/write status) output this is an output pin for the status signal pin that indicates whether the bus cycle is a read cycle or write cycle during external access. high level is set dur ing a read cycle and low level is set during a write cycle. the output changes in synchr onization with the rising edge of the cl ock in the t1 state of the bus cycle. high level is set when the timing sets the bus cycle as inactive. (iv) dstb (data strobe) output this is an output pin for the exter nal data bus?s access strobe signal. ou tput becomes active (low level) during the t2 and tw states of t he bus cycle. output becomes inac tive (high level) when the timing sets the bus cycle as inactive.
chapter 2 pin functions user?s manual u12768ej4v1ud 51 (v) astb (address strobe) output this is an output pin for the external address bus?s latch strobe signal. output becomes active (low level) in synchronization with the falling edge of t he clock during the t1 st ate of the bus cycle, and becomes inactive (high level) in synchronization wit h the falling edge of the clo ck during the t3 state of the bus cycle. output becomes inactive w hen the timing sets the bus cycle as inactive. (vi) hldak (hold acknowledge) output this is an output pin for the acknowledge signal t hat indicates high impedance status for the address bus, data bus, and control bus when the v850/sa1 receives a bus hold request. the address bus, data bus, and control bus are set to high impedance status when this signal is active. (vii) hldrq (hold request) input this is an input pin by which an external device requests the v850/sa1 to re lease the address bus, data bus, and control bus. this pin accepts asynchronous input for clkout. when this pin is active, the address bus, data bus, and control bus are set to high impedance status. this o ccurs either when the v850/sa1 completes execution of the current bus cycle or imm ediately if no bus cycle is being executed, then the hldak signal is set as active and the bus is released. (viii) wrl (write strobe low l evel data) output this is a write strobe signal output pin for the lower data in the exter nal 16-bit data bus. output occurs during the write cycle, similar to dstb. (ix) wrh (write strobe high level data) output this is a write strobe signal output pin for the higher data in the exter nal 16-bit data bus. output occurs during the write cycle, similar to dstb. (x) rd (read strobe) output this is a read strobe signal output pin for the external 16-bit data bus . output occurs during the read cycle, similar to dstb.
chapter 2 pin functions user?s manual u12768ej4v1ud 52 (10) p100 to p107 (port 10) 3-state i/o p100 to p107 constitute an 8-bit i/o port that c an be set to input or output in 1-bit units. p100 to p107 can also function as a real-time output port and an address bus (a5 to a12) when memory is expanded externally. p100 to p107 can be selected as norma l output or n-ch open-drain output. (a) port function p100 to p107 can be set to input or output in 1- bit units using the port 10 mode register (pm10). (b) alternate functions (i) rtp0 to rtp7 (real-time output port 0 to 7) output these pins comprise a real-time output port. (ii) a5 to a12 (address 5 to 12) output these comprise the address bus that is used for external access. thes e pins operate as the a5 to a12 bit address output pins within a 22-bit address. t he output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing se ts the bus cycle as inactive, the previous bus cycle?s address is retained. (11) p110 to p114 (port 11) 3-state i/o p110 to p114 constitute a 5-bit i/o port that can be set to i nput or output in 1-bit units. however, p114 is fixed as the xt1 input pin. p110 to p113 can also function as an address bus (a1 to a4) when memory is expanded externally. (a) port function p110 to p114 can be set to input or output in 1-bit uni ts using the port 11 mode regi ster (pm11). however, p114 is fixed as an input pin. (b) alternate functions (i) a1 to a4 (address 1 to 4) output these comprise the address bus that is used for external access. thes e pins operate as the lower 4-bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing se ts the bus cycle as inactive, the previous bus cycle?s address is retained. (ii) xt1 (crystal for subclock) input this is the pin that connects a resonator for subclock generation. the external clock can also be input to this pin. at this time, input a clock signal to the xt1 pin and its inverted signal to the xt2 pin.
chapter 2 pin functions user?s manual u12768ej4v1ud 53 (12) p120 (port 12) 3-state i/o p120 is a 1-bit i/o port that can be set to input or output in 1-bit units. p120 can also function as a control signal (wait) pin when a wait is in serted in the bus cycle. (a) port function p120 can be set to input or output us ing the port 12 mode register (pm12). (b) alternate functions (i) wait (wait) input this is an input pin for the control signal used to insert waits into the bus cycle. this pin is sampled at the falling edge of the clock during the t2 or tw state of the bus cycle. (13) clkout (clock out) output this is the pin used to output the bus clock generated internally. (14) reset (reset) input the reset pin is an asynchronous input and inputs a signal that has a constant low level width regardless of the status of the operating clock. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary init ialization/start operations, this pin can also be used to release a standby mode (halt, idle, or software stop mode). (15) x1 and x2 (crystal) these pins are used to connect the res onator that generates the main clock. these pins can also be used to input an external clock. when inputting an external clock, connect the x1 pin and leave the x2 pin open. (16) xt2 (crystal for subclock) this pin is used to connect the res onator that generates the subclock. (17) av dd (power supply for analog) this is the analog positive power supply pin for the a/d converter. be sure to keep the same potential as the v dd pin. (18) av ss (ground for analog) this is the ground pin for the a/d converter. (19) av ref (analog reference voltage) ? input this is the reference voltage supply pi n for the a/d converter. be sure to keep the same potential as the av dd pin. (20) bv dd (power supply for bus interface) this is the positive power supply pin for the bus interf ace and its alternate-function port. be sure to keep the same potential as the v dd pin. (21) bv ss (ground for bus interface) this is the ground pin for the bus inte rface and its alternate-function port.
chapter 2 pin functions user?s manual u12768ej4v1ud 54 (22) v dd (power supply) this is the positive power supply pin. all v dd pins should be connected to a positive power source. (23) v ss (ground) this is the ground pin. all v ss pins should be grounded. (24) v pp (programming power supply) this is the positive power supply pin used for flash memory programming mode. this pin is used in the pd70f3015b, 70f3015by, 70f3017a, and 70f3017ay. in normal operation mode, connect directly to v ss . (25) ic (internally connected) this is an internally connected pin used in the pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 703017a, and 703017ay. be sure to connect directly to v ss .
chapter 2 pin functions user?s manual u12768ej4v1ud 55 2.4 pin i/o circuits and recomme nded connection of unused pins (1/2) pin alternate function i/o circ uit type recommended connection method p00 nmi p01 to p04 intp0 to intp3 p05 intp4/adtrg p06 intp5/rtptrg p07 intp6 8-a p10 si0/sda note 10-a p11 so0 26 p12 sck0/scl note 10-a p13 si1/rxd0 8-a p14 so1/txd0 26 p15 sck1/asck0 10-a p20 si2 8-a p21 so2 26 p22 sck2 10-a p23 rxd1 8-a p24 txd1 5-a p25 asck1 p26, p27 ti2/to2, ti3/to3 p30, p31 ti00, ti01 p32, p33 ti10, ti11 8-a p34, p35 to0/a13, to1/a14 5-a p36 ti4/to4/a15 p37 ti5/to5 8-a input: independently connect to v dd or v ss via a resistor. output: leave open. p40 to p47 ad0 to ad7 p50 to p57 ad8 to ad15 p60 to p65 a16 to a21 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. p70 to p77 ani0 to ani7 p80 to p83 ani8 to ani11 9 connect to av dd or av ss . p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 hldrq 5 input: independently connect to bv dd or bv ss . output: leave open.
chapter 2 pin functions user?s manual u12768ej4v1ud 56 (2/2) pin alternate function i/o circ uit type recommended connection method p100 to p107 rtp0/a5 to rtp7/a12 26 p110 to p113 a1 to a4 5 input: independently connect to v dd or v ss via a resistor. output: leave open. p114 xt1 16-a c onnect to v ss . p120 wait 5 i nput: connect to bv dd or bv ss via a resistor. output: leave open. av ref ? ? connect to av ss . clkout ? 4 leave open. ic note 1 ? ? directly connect to v ss . reset ? 2 ? v pp note 2 ? ? connect to v ss . x2 ? ? leave open (when external clock is input to x1 pin). xt2 ? 16-a leave open. notes 1. pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 703017a, and 703017ay only 2. pd70f3015b, 70f3015by, 70f3017a, and 70f3017ay only
chapter 2 pin functions user?s manual u12768ej4v1ud 57 2.5 pin i/o circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics type 4 push-pull output that can be set to high impedance output (both p-ch and n-ch off). type 5 type 5-a in data output disable p-ch out v dd n-ch data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable type 8-a data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable type 9 in comparator + ? v ref (threshold voltage) p-ch n-ch input enable
chapter 2 pin functions user?s manual u12768ej4v1ud 58 (2/2) type 10-a type 26 data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable open drain type 16-a xt1 xt2 data output disable open drain p-ch in/out v dd n-ch p-ch v dd pullup enable
user?s manual u12768ej4v1ud 59 chapter 3 cpu functions the cpu of the v850/sa1 is based on risc architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 features ? minimum instruction execution time: 50 ns (@ internal 20 mhz operation) 58.8 ns (@ internal 17 mhz operation) 30.5 s (@ internal 32.768 khz operation) ? address space: 16 mb linear (physical address space: 4 mb) ? thirty-two 32-bit general-purpose registers ? internal 32-bit architecture ? five-stage pipeline control ? multiply/divide instructions ? saturated operation instructions ? one-clock 32-bit shift instruction ? load/store instruction with long/short format ? four types of bit manipulation instructions set1 clr1 not1 tst1
chapter 3 cpu functions user?s manual u12768ej4v1ud 60 3.2 cpu register set the cpu registers of the v850/sa1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. all the regist ers have a 32 bits width. for details, refer to v850 series architecture user?s manual . figure 3-1. cpu register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 zero register reserved for address register stack pointer (sp) global pointer (gp) text pointer (tp) element pointer (ep) link pointer (lp) pc program counter psw program status word ecr exception cause register fepc fepsw fatal error pc fatal error psw eipc eipsw exception/interrupt pc exception/interrupt psw 31 0 31 0 31 0 31 0 31 0 31 0 system register set program register set
chapter 3 cpu functions user?s manual u12768ej4v1ud 61 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are av ailable. any of these regi sters can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instructions, so care must be ex ercised when using these registers. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. therefore, before using these registers, their contents must be saved so that they are not lost. t he contents must be rest ored to the registers after the registers have been used. r2 is sometimes us ed by the real-time os. when the real-time os to be used is not using r2, r2 can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved regist er working register for gene rating 32-bit immediate r2 address/data variable register (when the real-time os to be used is not using r2) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area note r6 to r29 address/dat a variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution note area in which program code is mapped. (2) program counter (pc) this register holds the address of the instruction under execution. the lower 24 bits of this register are valid, and bits 31 to 24 are fixed to 0. if a carry occurs from bit 23 to bit 24, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. after reset: 00000000h symbol 31 24 23 1 0 pc fixed to 0 instruction address under execution 0
chapter 3 cpu functions user?s manual u12768ej4v1ud 62 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. table 3-2. system register numbers no. system register name usage operation 0 eipc 1 eipsw interrupt status saving registers thes e registers save the pc and psw when an exception or interrupt occurs. because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. 2 fepc 3 fepsw nmi status saving registers these regist ers save the pc and psw when an nmi occurs. 4 ecr interrupt source register if an excepti on, maskable interrupt, or nmi occurs, this register will contain information referencing the interrupt source. the higher 16 bits of this register are called fecc, to which the exception code of the nmi is set. the lower 16 bits are called eicc, to which the exception code of the exception/interrupt is set. 5 psw program status word the program status word is a collection of flags that indicate the program status (instruction execution result) and cpu status. 6 to 31 reserved to read/write these system r egisters, specify the system register number indicated by the system register load/store instruction (lds r or stsr instruction). (1) interrupt source register (ecr) after reset: 00000000h symbol 31 16 15 0 ecr fecc eicc fecc exception code of nmi (for the exception code, refer to table 5-1 .) eicc exception code of exception/interrupt
chapter 3 cpu functions user?s manual u12768ej4v1ud 63 (2) program status word (psw) (1/2) after reset: 00000020h 31 8 7 6 5 4 3 2 1 0 psw rfu np ep id sat cy ov s z rfu reserved field (fixed to 0). np non-maskable interrupt (nmi) servicing status 0 nmi servicing not under execution. 1 nmi servicing under execution. this flag is set (1) when an nmi is acknowledged, and disables multiple interrupts. for details, refer to 5.2.3 np flag. ep exception processing status 0 exception processing not under execution. 1 exception processing under execution. this flag is set (1) when an exception is generated. interrupt requests can be acknowledged when this bit is set. for details, refer to 5.4.3 ep flag. id maskable interrupt servicing specification 0 maskable interrupt acknowledgement enabled. 1 maskable interrupt acknowledgement disabled. this flag is set (1) when a maskable in terrupt request is acknowledged. for details, refer to 5.3.6 id flag.
chapter 3 cpu functions user?s manual u12768ej4v1ud 64 (2/2) sat note saturation detection of operation result of saturation operation instruction 0 not saturated. this flag is not cleared (0) if the result of saturated operation instruction execution is not saturated while this flag is set (1). to clear (0) this flag, write the psw directly. 1 saturated. cy detection of carry or borrow of operation result 0 overflow has not occurred. 1 overflow occurred. ov note detection of overflow during operation 0 overflow has not occurred. 1 overflow occurred. s note detection of operation result positive/negative 0 the operation result was positive or 0. 1 the operation result was negative. z detection of operation result zero 0 the operation result was not 0. 1 the operation result was 0. note the result of a saturation-processed operation is de termined by the contents of the ov and s bits in the saturation operation. simply setting (1) the ov bit will set (1) the sat bit in a saturation operation. flag status status of operation result sat ov s saturation-processed operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (not exceeding the maximum) 0 negative (not exceeding the maximum) retains the value before operation 0 1 operation result itself
chapter 3 cpu functions user?s manual u12768ej4v1ud 65 3.3 operation modes the v850/sa1 has the foll owing operation modes. (1) normal operation mode (single-chip mode) after the system has been released from the reset status , the pins related to the bus interface are set to port mode, execution branches to the reset entry address of the internal rom, and instruction processing written in the internal rom is started. the external expansion mode in which an external device can be connected to external memory area is enabled by setting the me mory expansion mode register (mm) by an instruction. (2) flash memory programming mode this mode is provided only in the pd70f3015b, 70f3015by, 70f3017a, and 70f3017ay. the internal flash memory is programmable or erasable when the v pp voltage is applied to the v pp pin. v pp operation mode 0 normal operation mode 7.8 v flash memory programming mode v dd setting prohibited
chapter 3 cpu functions user?s manual u12768ej4v1ud 66 3.4 address space 3.4.1 cpu address space the cpu of the v850/sa1 is of 32-bit architecture and s upports up to 4 gb of linear address space (data space) during operand addressing (data access). when referencing instruction addresses, linear address space (program space) of up to 16 mb is support ed (physical address space: 4 mb). the cpu address space is shown below. figure 3-2. cpu address space ffffffffh program area (16 mb linear) data area (4 gb linear) 01000000h 00ffffffh 00000000h
chapter 3 cpu functions user?s manual u12768ej4v1ud 67 3.4.2 image the cpu supports 4 gb of ?virtual ? addressing space, or 256 memory bl ocks, each containing 16 mb memory locations. in actuality, the same 16 mb block is access ed regardless of the values of bits 31 to 24 of the cpu address. figure 3-3 shows the ima ge of the virtual addressing space. because the higher 8 bits of a 32-bit cpu address are ignored and the cpu address is only seen as a 24-bit external physical address, the physical location xx000000h is equally referenced by multiple address values 00000000h, 0100000 0h, 02000000h, ... fe 000000h, ff000000h. figure 3-3. image on address space ffffffffh ff000000h feffffffh image cpu address space image image image image fe000000h fdffffffh 02000000h 01ffffffh 01000000h 00ffffffh 00000000h physical address space on-chip peripheral i/o internal ram (access prohibited) internal rom xxffffffh xx000000h
chapter 3 cpu functions user?s manual u12768ej4v1ud 68 3.4.3 wraparound of cpu address space (1) program space of the 32 bits of the pc (program count er), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. even if a carry or borrow occurs from bit 23 to bit 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0. therefore, the lower-limit a ddress of the program space, address 00000000h, and the upper-limit address 00ffffffh are contiguous addresses, an d the program space is wrapped around at the boundar y of these addresses. caution no instruction can be fetched from th e 4 kb area of 00fff000h to 00ffffffh because this area is defined as periphera l i/o area. therefore, do not execute any branch operation instructions in which the destination addres s will reside in any part of this area. figure 3-4. program space 00fffffeh 00ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of operand address calculati on that exceeds 32 bits is ignored. therefore, the lowe r-limit address of the program space, addr ess 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. figure 3-5. data space fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction
chapter 3 cpu functions user?s manual u12768ej4v1ud 69 3.4.4 memory map the v850/sa1 reserves areas as shown below. figure 3-6. memory map xxffffffh on-chip peripheral i/o area internal ram area (reserved) internal flash memory/ internal rom area on-chip peripheral i/o area internal ram area external memory area internal flash memory/ internal rom area single-chip mode single-chip mode (external expansion mode) 16 mb 1 mb 4 kb xxfff000h xxffefffh xx100000h xx0fffffh xx000000h xxffc000h xxffbfffh 12 kb
chapter 3 cpu functions user?s manual u12768ej4v1ud 70 3.4.5 area (1) internal rom/intern al flash memory area an area of 1 mb maximum is reserved for the in ternal rom/internal flash memory area. (a) memory map <1> pd703014a, 703014ay, 703014b, 703014by 64 kb is provided at addre sses xx000000h to xx00ffffh. addresses xx010000h to xx0fffffh are access-prohibited area. figure 3-7. internal rom area (64 kb) xx010000h xx00ffffh xx000000h xx0fffffh access-prohibited area internal rom <2> pd703015a, 703015ay, 703015b, 703015by, 70f3015b, 70f3015by 128 kb is provided at addres ses xx000000h to xx01ffffh. addresses xx020000h to xx0fffffh are access-prohibited area. figure 3-8. internal rom area (128 kb) xx020000h xx01ffffh xx000000h xx0fffffh access-prohibited area internal rom
chapter 3 cpu functions user?s manual u12768ej4v1ud 71 <3> pd703017a, 703017ay, 70f3017a, 70f3017ay 256 kb is provided at addres ses xx000000h to xx03ffffh. addresses xx040000h to xx0fffffh are access-prohibited area. figure 3-9. internal rom/inte rnal flash memory area (256 kb) xx040000h xx03ffffh xx000000h xx0fffffh access-prohibited area internal rom/ internal flash memory
chapter 3 cpu functions user?s manual u12768ej4v1ud 72 (b) interrupt/exception table the v850/sa1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addr esses is called an interrupt/excepti on table, which is located in the internal rom/on-chip flash memory area. when an inte rrupt/exception request is granted, execution jumps to the handler address, and the pr ogram written at that memory addr ess is executed. the sources of interrupts/exceptions, and the corresp onding addresses are shown below. table 3-3. interrupt/exception table start address of interrupt/exception table interrupt/exception source 00000000h reset 00000010h nmi 00000020h intwdt 00000040h trap0n (n = 0 to f) 00000050h trap1n (n = 0 to f) 00000060h ilgop 00000080h intwdtm 00000090h intp0 000000a0h intp1 000000b0h intp2 000000c0h intp3 000000d0h intp4 000000e0h intp5 000000f0h intp6 00000100h intwti 00000110h inttm00 00000120h inttm01 00000130h inttm10 00000140h inttm11 00000150h inttm2 00000160h inttm3 00000170h inttm4 00000180h inttm5 00000190h intiic0 note /intcsi0 000001a0h intser0 000001b0h intsr0/intcsi1 000001c0h intst0 000001d0h intcsi2 000001e0h intser1 000001f0h intsr1 00000200h intst1 00000210h intad 00000220h intdma0 00000230h intdma1 00000240h intdma2 00000250h intwt note available only in the pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay.
chapter 3 cpu functions user?s manual u12768ej4v1ud 73 (2) internal ram area up to 12 kb is reserved for the internal ram area. (a) pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 70f3015b, 70f3015by 4 kb is provided at addresses xxffe000h to xxffefffh. addresses xxffc000h to xxffdfffh are access-prohibited area. figure 3-10. internal ram area (4 kb) xxffe000h xxffdfffh xxffc000h xxffefffh access-prohibited area internal ram (b) pd703017a, 703017ay, 70f3017a, 70f3017ay 8 kb is provided at addresses xxffd000h to xxffefffh. addresses xxffc000h to xxffcfffh are access-prohibited area. figure 3-11. internal ram area (8 kb) xxffd000h xxffcfffh xxffc000h xxffefffh access-prohibited area internal ram
chapter 3 cpu functions user?s manual u12768ej4v1ud 74 (3) on-chip peripheral i/o area a 4 kb area of addresses fff000h to ffffffh is reserved as an on-chip peripheral i/o area. the v850/sa1 is provided with a 1 kb area of addresse s fff000h to fff3ffh as a physical on-chip peripheral i/o area, and its image can be seen on the rest of the ar ea (fff400h to ffffffh). peripheral i/o registers associated with operation mo de specification and state mo nitoring for the on-chip peripherals are all memory-mapped to t he on-chip peripheral i/o area. program fetches are not allowed in this area. figure 3-12. on-chip peripheral i/o area xxffffffh xxfffc00h xxfffbffh xxfff800h xxfff7ffh xxfff400h xxfff3ffh xxfff000h image image image physical on-chip peripheral i/o 3ffh 000h image peripheral i/o cautions 1. the least significant bit of an address is not decoded since all regi sters reside at an even address. if an odd address (2n + 1) in the pe ripheral i/o area is refe renced (accessed in byte units), the register at the next lowest even address (2 n) will be accessed. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined, if the access is a read operation. if a write access is made, only the data in the lower 8 bits is written to the register. 3. if a register at address n that can be acc essed only in halfword unit s is accessed in word units, the operation is replaced with two halfword operations. the first operation (lower 16 bits) accesses the register at address n and the second operati on (higher 16 bits) accesses the register at address n + 2. 4. if a register at address n that can be accessed in word units is accessed with a word operation, the operation is replaced with two halfword operations. the first operation (lower 16 bits) accesses the regi ster at address n and the sec ond operation (higher 16 bits) accesses the register at address n + 2. 5. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed.
chapter 3 cpu functions user?s manual u12768ej4v1ud 75 (4) external memory area the v850/sa1 can use an ar ea of up to 16 mb (xx100000h to xxffb fffh) for external me mory accesses (in single-chip mode: during external expansion). 64 kb, 256 kb, 1 mb, or 4 mb of physical external memory can be allocated when the external expansion mode is specified. in the area of other than the physical external memory, the image of the physical external memory can be seen. the internal ram area and on-chip peripheral i/o ar ea are not subject to external memory access. figure 3-13. external memory area (w hen expanded to 64 kb, 256 kb, or 1 mb) xxffffffh xx000000h physical external memory xffffh x0000h on-chip peripheral i/o internal ram image image image internal rom xxffbfffh xx100000h external memory
chapter 3 cpu functions user?s manual u12768ej4v1ud 76 figure 3-14. external memory area (when expanded to 4 mb) xxffffffh xxffbfffh image on-chip peripheral i/o internal ram image image image internal rom xxc00000h xxbfffffh xx800000h xx7fffffh xx100000h xx0fffffh xx400000h xx3fffffh xx000000h physical external memory external memory 3fffffh 000000h
chapter 3 cpu functions user?s manual u12768ej4v1ud 77 3.4.6 external expansion mode the v850/sa1 allows external devices to be connected to t he external memory space by using the pins of ports 4, 5, 6, and 9. to connect an external device, the port pins must be set to the external expansion mode by using the memory expansion mode register (mm). the address bus (a1 to a15) is set to multiplexed bus ou tput with the data bus (d1 to d15), though separate bus output is also possible by setting the me mory address output mode register (mam) (see ie-703017-mc-emi user?s manual for debugging when using the separate bus). because the v850/sa1 is fixed to single-chip mode in t he normal operation mode, the port/control mode alternate- function pins enter the port mode, and the external memo ry cannot be used. when the external memory is used (external expansion mode), specify the mm register or mam register by the program (memory area is set by the mm register). (1) memory expansion mode register (mm) this register sets the mode of each pin of ports 4, 5, 6, and 9. in t he external expansion mode, an external device can be connected to an external memory area of up to 4 mb. however, an external device cannot be connected to the internal ram area, on-chip peripheral i/o area, and internal rom area in the single-chip mode (and even if the external device is connec ted physically, it cannot be accessed). the mm register can be read/written in 8-bit or 1-bit units. however, bits 4 to 7 are fixed to 0. after reset: 00h r/w address: fffff04ch symbol 7 6 5 4 3 2 1 0 mm 0 0 0 0 mm3 mm2 mm1 mm0 mm3 p95 and p96 operation modes 0 port mode 1 external expansion mode (hldak: p95, hldrq: p96) mm2 mm1 mm0 address space port 4 port 5 port 6 port 9 0 0 0 ? port mode 0 1 1 64 kb ad0 to ad8 to lben, expansion mode ad7 ad15 uben, 1 0 0 256 kb a16, r/w, dstb, expansion mode a17 astb, 1 0 1 1 mb a18, wrl, expansion mode a19 wrh, rd 1 1 4 mb a20, expansion mode a21 other than above rfu (reserved) caution when switching to the exter nal expansion mode, the p93 and p94 bi ts of port 9 (p9) must be set to 1 before switching. remark for details of the operation of each port pin, refer to 2.3 description of pin functions .
chapter 3 cpu functions user?s manual u12768ej4v1ud 78 (2) memory address output mode register (mam) this register sets the mode of each pin of ports 3, 10, and 11. separate output can be set for the address bus (a1 to a15) in the external expansio n mode. separate bus output is outpu t to p34 to p36, p100 to p107, and p110 to p113. set the separate bus output according to the following procedure. (i) set to output mode (pmn bit = 0) after setting port m, which will be used for separate output, to 0 output (pn bit = 0). (ii) turn this function off if the ports to be used as the separate bus are being used as alternate-function pins other than those of the separate bus. (iii) set the memory address output register (mam). (iv) set the memory expansion mode register (mm) (refer to 3.4.6 (1) memory expansion mode register (mm) ). the mam register can be written in 8-bi t units. if read, undefined values will be read. however, bits 3 to 7 are fixed to 0. remark when m = 3: n = 34 to 36 when m = 10: n = 100 to 107 when m = 11: n = 110 to 113 after reset: 00h w address: fffff068h symbol 7 6 5 4 3 2 1 0 mam 0 0 0 0 0 mam2 mam1 mam0 mam2 mam1 mam0 address space port 11 port 10 port 3 0 0 0 ? port mode 0 1 0 32 bytes 0 1 1 512 bytes 1 0 0 8 kb 1 0 1 16 kb 1 1 0 32 kb 1 1 1 64 kb a1 to a4 a5 to a8 a9 to a12 a13 a14 a15 caution an in-circuit emulator cannot be used to debug the memory addres s output mode register (mam). also, the separate bus ca nnot be switched to by setting the mam register by software. for details, refer to ie- 703017-mc-emi user?s manual. remark for details of the operation of each port pin, refer to 2.3 description of pin functions .
chapter 3 cpu functions user?s manual u12768ej4v1ud 79 3.4.7 recommended use of address space the architecture of the v850/sa1 r equires that a register that serves as a pointer be secured for address generation in operand data accessing of the data space. the address in this pointer register 32 kb can be accessed directly from an instruction. however, the general-purpose register s that can be used as a point er register are limited. therefore, by minimizing deterioration of the address calc ulation performance when changing the pointer value, the number of usable general-purpose registers for handling va riables is maximized, and the program size can be minimized because instructions for calculat ing pointer addresses are not required. to enhance the efficiency of using the pointer in connec tion with the memory map of the v850/sa1, the following points are recommended. (1) program space of the 32 bits of the pc (program count er), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. therefore, a continuous 16 mb space, starting from address 00000000 h, unconditionally corresponds to the memory map of the program space. (2) data space for the efficient use of resources to be performed using the wraparound feature of the da ta space, the continuous 8 mb address spaces 00000000h to 007fffffh and ff800000h to ffffffffh of the 4 gb cpu are used as the data space. with the v850/sa1, the 16 mb physical address space is seen as 256 images in the 4 gb cpu address space. the highest bit (bit 23) of this 24-bit ad dress is assigned as an address sign-extended to 32 bits. application example of wraparound for example, when r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced with the sign-extend ed 16-bit displacement value. by mapping the external memory in the 16 kb area in figure 3-15, all resources including on-chip hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by the ha rdware, and eliminates the need for additional registers for the pointer. figure 3-15. application example of wraparound internal rom area on-chip peripheral i/o area internal ram area 4 kb 12 kb 0001ffffh 00007fffh (r =) 00000000h fffff000h ffffc000h external memory area 16 kb ffff8000h 32 kb
chapter 3 cpu functions user?s manual u12768ej4v1ud 80 figure 3-16. recommended memory map ffffffffh fffff400h fffff3ffh 00000000h 16 mb 8 mb internal rom area internal rom area external memory area internal ram area on-chip peripheral i/o area note program space data space on-chip peripheral i/o area internal ram area external memory area on-chip peripheral i/o area internal ram area access-prohibited area external memory area external memory area internal rom area xxffffffh xxfff400h xxfff3ffh xxfff000h xxffefffh xxffc000h xxffbfffh xxffd000h xxffcfffh xx100000h xx0fffffh xx040000h xx03ffffh xx800000h xx7fffffh xx000000h fffff000h ffffefffh ffffc000h ffffbfffh ff800000h ff7fffffh 01000000h 00ffffffh 00fff000h 00ffefffh 00ffc000h 00ffbfffh 00800000h 007fffffh 00100000h 000fffffh 00040000h 0003ffffh note this area cannot be used as a program area. remarks 1. the arrows indicate the recommended area. 2. this is the recommended memory map for the pd703017a and 703017ay.
chapter 3 cpu functions user?s manual u12768ej4v1ud 81 3.4.8 peripheral i/o registers (1/5) bit units for manipulation after reset address function register name symbol r/w 1 bit 8 bits 16 bits fffff000h port 0 p0 r/w 00h note fffff002h port 1 p1 r/w 00h note fffff004h port 2 p2 r/w 00h note fffff006h port 3 p3 r/w 00h note fffff008h port 4 p4 r/w 00h note fffff00ah port 5 p5 r/w 00h note fffff00ch port 6 p6 r/w 00h note fffff00eh port 7 p7 r undefined fffff010h port 8 p8 r undefined fffff012h port 9 p9 r/w 00h note fffff014h port 10 p10 r/w 00h note fffff016h port 11 p11 r/w 00h note fffff018h port 12 p12 r/w 00h note fffff020h port 0 mode register pm0 r/w ffh fffff022h port 1 mode register pm1 r/w 3fh fffff024h port 2 mode register pm2 r/w ffh fffff026h port 3 mode register pm3 r/w ffh fffff028h port 4 mode register pm4 r/w ffh fffff02ah port 5 mode register pm5 r/w ffh fffff02ch port 6 mode register pm6 r/w 3fh fffff032h port 9 mode register pm9 r/w 7fh fffff034h port 10 mode register pm10 r/w ffh fffff036h port 11 mode register pm11 r/w 1fh fffff038h port 12 mode register pm12 r/w 01h fffff04ch memory expansion mode register mm r/w 00h fffff058h port 12 mode control register pmc12 r/w 00h fffff060h data wait control register dwc r/w ffffh fffff062h bus cycle control register bcc r/w aaaah fffff064h system control register syc r/w 00h fffff068h memory address output mode register mam w 00h fffff070h power save control register psc r/w c0h fffff074h processor clock control register pcc r/w 03h fffff078h system status register sys r/w 00h fffff080h pull-up resistor option register 0 pu0 r/w 00h fffff082h pull-up resistor option register 1 pu1 r/w 00h note resetting initializes registers to input mode and the pin level is read. output latches are initialized to 00h.
chapter 3 cpu functions user?s manual u12768ej4v1ud 82 (2/5) bit units for manipulation after reset address function register name symbol r/w 1 bit 8 bits 16 bits fffff084h pull-up resistor option register 2 pu2 r/w 00h fffff086h pull-up resistor option register 3 pu3 r/w 00h fffff094h pull-up resistor option register 10 pu10 r/w 00h fffff096h pull-up resistor option register 11 pu11 r/w 00h fffff0a2h port 1 function register pf1 r/w 00h fffff0a4h port 2 function register pf2 r/w 00h fffff0b4h port 10 function register pf10 r/w 00h fffff0c0h rising edge specification register 0 egp0 r/w 00h fffff0c2h falling edge specification register 0 egn0 r/w 00h fffff100h interrupt control register wdtic r/w 47h fffff102h interrupt control register pic0 r/w 47h fffff104h interrupt control register pic1 r/w 47h fffff106h interrupt control register pic2 r/w 47h fffff108h interrupt control register pic3 r/w 47h fffff10ah interrupt control register pic4 r/w 47h fffff10ch interrupt control register pic5 r/w 47h fffff10eh interrupt control register pic6 r/w 47h fffff110h interrupt control register wtiic r/w 47h fffff112h interrupt control register tmic00 r/w 47h fffff114h interrupt control register tmic01 r/w 47h fffff116h interrupt control register tmic10 r/w 47h fffff118h interrupt control register tmic11 r/w 47h fffff11ah interrupt control register tmic2 r/w 47h fffff11ch interrupt control register tmic3 r/w 47h fffff11eh interrupt control register tmic4 r/w 47h fffff120h interrupt control register tmic5 r/w 47h fffff122h interrupt control register csic0 r/w 47h fffff124h interrupt control register seric0 r/w 47h fffff126h interrupt control register csic1 r/w 47h fffff128h interrupt control register stic0 r/w 47h fffff12ah interrupt control register csic2 r/w 47h fffff12ch interrupt control register seric1 r/w 47h fffff12eh interrupt control register sric1 r/w 47h fffff130h interrupt control register stic1 r/w 47h fffff132h interrupt control register adic r/w 47h fffff134h interrupt control register dmaic0 r/w 47h
chapter 3 cpu functions user?s manual u12768ej4v1ud 83 (3/5) bit units for manipulation after reset address function register name symbol r/w 1 bit 8 bits 16 bits fffff136h interrupt control register dmaic1 r/w 47h fffff138h interrupt control register dmaic2 r/w 47h fffff13ah interrupt control register wtic r/w 47h fffff166h in-service priority register ispr r 00h fffff170h command register prcmd w undefined fffff180h dma peripheral i/o address register 0 dioa0 r/w undefined fffff182h dma internal ram address register 0 dra0 r/w undefined fffff184h dma byte count register 0 dbc0 r/w undefined fffff186h dma channel control register 0 dchc0 r/w 00h fffff190h dma peripheral i/o address register 1 dioa1 r/w undefined fffff192h dma internal ram address register 1 dra1 r/w undefined fffff194h dma byte count register 1 dbc1 r/w undefined fffff196h dma channel control register 1 dchc1 r/w 00h fffff1a0h dma peripheral i/o address register 2 dioa2 r/w undefined fffff1a2h dma internal ram address register 2 dra2 r/w undefined fffff1a4h dma byte count register 2 dbc2 r/w undefined fffff1a6h dma channel control register 2 dchc2 r/w 00h fffff1f4h flash programming mode control register note 1 flpmc r/w note 2 fffff200h 16-bit timer register 0 tm0 r 0000h fffff202h 16-bit capture/compare register 00 cr00 note 3 0000h fffff204h 16-bit capture/compare register 01 cr01 note 3 0000h fffff206h prescaler mode register 0 prm0 r/w 00h fffff208h 16-bit timer mode control register 0 tmc0 r/w 00h fffff20ah capture/compare control register 0 crc0 r/w 00h fffff20ch timer output control register 0 toc0 r/w 00h fffff20eh prescaler mode register 01 prm01 r/w 00h fffff210h 16-bit timer register 1 tm1 r 0000h fffff212h 16-bit capture/compare register 10 cr10 note 3 0000h fffff214h 16-bit capture/compare register 11 cr11 note 3 0000h fffff216h prescaler mode register 1 prm1 r/w 00h fffff218h 16-bit timer mode control register 1 tmc1 r/w 00h fffff21ah capture/compare control register 1 crc1 r/w 00h fffff21ch timer output control register 1 toc1 r/w 00h notes 1. valid only for the pd70f3015b, 70f3015by, 70f3017a, and 70f3017ay. 2. in single-chip mode: 18h or 38h in flash memory programming mode: 1ch or 3ch 3. in compare mode: r/w in capture mode: r
chapter 3 cpu functions user?s manual u12768ej4v1ud 84 (4/5) bit units for manipulation after reset address function register name symbol r/w 1 bit 8 bits 16 bits fffff21eh prescaler mode register 11 prm11 r/w 00h fffff240h 8-bit counter 2 tm2 r 00h fffff242h 8-bit compare register 2 cr20 r/w 00h fffff244h timer clock select register 2 tcl2 r/w 00h fffff246h 8-bit timer mode control register 2 tmc2 r/w 04h note fffff24ah 16-bit counter 23 (only when connected in cascade) tm23 r 0000h fffff24ch 16-bit compare regi ster 23 (only when connected in cascade) cr23 r/w 0000h fffff24eh timer clock select register 21 tcl21 r/w 00h fffff250h 8-bit counter 3 tm3 r 00h fffff252h 8-bit compare register 3 cr30 r/w 00h fffff254h timer clock select register 3 tcl3 r/w 00h fffff256h 8-bit timer mode control register 3 tmc3 r/w 04h note fffff25eh timer clock select register 31 tcl31 r/w 00h fffff260h 8-bit counter 4 tm4 r 00h fffff262h 8-bit compare register 4 cr40 r/w 00h fffff264h timer clock select register 4 tcl4 r/w 00h fffff266h 8-bit timer mode control register 4 tmc4 r/w 04h note fffff26ah 16-bit counter 45 (only when connected in cascade) tm45 r 0000h fffff26ch 16-bit compare regi ster 45 (only when connected in cascade) cr45 r/w 0000h fffff26eh timer clock select register 41 tcl41 r/w 00h fffff270h 8-bit counter 5 tm5 r 00h fffff272h 8-bit compare register 5 cr50 r/w 00h fffff274h timer clock select register 5 tcl5 r/w 00h fffff276h 8-bit timer mode control register 5 tmc5 r/w 04h note fffff27eh timer clock select register 51 tcl51 r/w 00h fffff2a0h serial i/o shift register 0 sio0 r/w 00h fffff2a2h serial operation mode register 0 csim0 r/w 00h fffff2a4h serial clock sele ct register 0 csis0 r/w 00h fffff2b0h serial i/o shift register 1 sio1 r/w 00h fffff2b2h serial operation mode register 1 csim1 r/w 00h fffff2b4h serial clock sele ct register 1 csis1 r/w 00h fffff2c0h serial i/o shift register 2 sio2 r/w 00h fffff2c2h serial operation mode register 2 csim2 r/w 00h note although the hardware status is initialized to 04h, 00h will be read out in a read operation.
chapter 3 cpu functions user?s manual u12768ej4v1ud 85 (5/5) bit units for manipulation after reset address function register name symbol r/w 1 bit 8 bits 16 bits fffff2c4h serial clock sele ct register 2 csis2 r/w 00h fffff300h asynchronous serial interface mode register 0 asim0 r/w 00h fffff302h asynchronous serial interface status register 0 asis0 r 00h fffff304h baud rate generator control register 0 brgc0 r/w 00h fffff306h transmission shift register 0 txs0 w ffh fffff308h reception buffer register 0 rxb0 r ffh fffff30eh baud rate generator mode control register 00 brgmc0 r/w 00h fffff310h asynchronous serial interface mode register 1 asim1 r/w 00h fffff312h asynchronous serial interface status register 1 asis1 r 00h fffff314h baud rate generator control register 1 brgc1 r/w 00h fffff316h transmission shift register 1 txs1 w ffh fffff318h reception buffer register 1 rxb1 r ffh fffff31eh baud rate generator mode control register 1 brgmc1 r/w 00h fffff320h baud rate generator mode control register 01 brgmc01 r/w 00h fffff340h iic control register 0 note iicc0 r/w 00h fffff342h iic status register 0 note iics0 r 00h fffff344h iic clock select register 0 note iiccl0 r/w 00h fffff346h slave address register 0 note sva0 r/w 00h fffff348h iic shift register 0 note iic0 r/w 00h fffff34ah iic function expansion register 0 note iicx0 r/w 00h fffff360h watch timer mode register wtm r/w 00h fffff380h oscillation stabilization time select register osts r/w 04h fffff382h watchdog timer clock se lect register wdcs r/w 00h fffff384h watchdog timer mode register wdtm r/w 00h fffff3a0h real-time output buffer register l rtbl r/w 00h fffff3a2h real-time output buffer register h rtbh r/w 00h fffff3a4h real-time output port mode register rtpm r/w 00h fffff3a6h real-time output port control register rtpc r/w 00h fffff3c0h a/d converter mode register adm r/w 00h fffff3c2h analog input channel specification register ads r/w 00h fffff3c4h a/d conversion result register adcr r 0000h fffff3c6h a/d conversion result r egister h (higher 8 bits) adcrh r 00h note valid only for the pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay.
chapter 3 cpu functions user?s manual u12768ej4v1ud 86 3.4.9 specific registers specific registers are registers that are protected from being written wit h illegal data due to erroneous program execution, etc. the wr ite access of these specific regi sters is executed in a specific sequence, and if abnormal write operations occur, it is checked by t he prerr bit of the system status regi ster (sys). the v850/sa1 has three specific registers, the power save control register (psc), processor cl ock control register (pcc), and flash programming mode control register (flpmc). for details of the psc register, refer to 6.3.1 (2) power save control register (psc), for details of the pcc register, refer to 6.3.1 (1) processor clock control register (pcc), and for details of the flpmc register, refer to 16.7.12 flash programming mode control register (flpmc). the following sequence shows the data se tting of the specific registers. <1> disable dma operation. <2> set the psw np bit to 1 (interrupt disabled). <3> write any 8-bit data in the command register (prcmd). <4> write the set data in the specific regi sters (using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> return the psw np bit to 0 (interrupt disable canceled). <6> if necessary, enable dma operation. no special sequence is required when reading the specific registers. cautions 1. if an interrupt request or a dma re quest is acknowledged between the time prcmd is generated (<3>) and the specific register write operation (<4>) that follows immediately after, the write operation to the specific register is not performed and a protection error (prerr bit of sys register is 1) may occur. therefore, set the np bit of psw to 1 (<2>) to disable the acknowledgement of int/nmi or to disable dma transfer. the above also applies when a bit manipulation instruction is used to set a specific register. a description example is given below. [description example]: in case of pcc register ldsr rx.5 ; np bit = 1 st.b r0, prcmd [r0] ; write to prcmd st.b rd, pcc [r0] ; pcc register setting ldsr ry, 5 ; np bit = 0 . . . rx: value to be written to psw ry: value to be written back to psw rd: value to be set to pcc when saving the value of psw, the value of psw prior to setting the np bit must be transferred to the ry register.
chapter 3 cpu functions user?s manual u12768ej4v1ud 87 cautions 2. always stop the dma pr ior to accessing speci fic registers. 3. when data is set to the psc register in orde r to set the idle mode or software stop mode, a dummy instruction must be inserted so that the routine after rele asing the idle/software stop mode is executed correctly. for deta ils, refer to 6.6 cautions on power save function. 4. when the flspm bit of the flpmc register is manipulated to swit ch between the normal mode and the flash memory self-programmi ng mode, a dummy instruction must be inserted. for details, refer to 16.7.12 flash programming mode contro l register (flpmc).
chapter 3 cpu functions user?s manual u12768ej4v1ud 88 (1) command register (prcmd) the command register (prcmd) is a register used when writ e-accessing a specific register to prevent incorrect writing to the specific register due to the erroneous program execution. this register can be written in 8-bit uni ts. it becomes undefined in a read cycle. occurrence of illegal write oper ations can be checked by the prerr bit of the sys register. after reset: undefined w address: fffff170h symbol 7 6 5 4 3 2 1 0 prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 regn registration code 0/1 any 8-bit data remark n = 0 to 7 (2) system status register (sys) this register is allocated with status flags showing the operating state of the entire system. this register can be read/written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff078h symbol 7 6 5 4 3 2 1 0 sys 0 0 0 prerr 0 0 0 0 prerr detection of protection error 0 protection error did not occur 1 protection error occurred the operating conditions of prerr flag are shown below. (a) set conditions (prerr = 1) (1) when a write operation to the spec ific register took place in a stat e where the store in struction operation for the recent peripheral i/o was not a write operation to the prcmd register (2) when the first store instruction operation followin g a write operation to the prcmd register is to any peripheral i/o register (including t he prcmd register and sys register) apart from specific registers (b) reset conditions (prerr = 0) (1) when 0 is written to the prerr flag of the sys register note (2) at system reset note if 0 is written to the prerr flag immediately after writing to the prcmd regi ster, the prerr flag is set to 1 (because the sys register is not a specific register).
user?s manual u12768ej4v1ud 89 chapter 4 bus control function the v850/sa1 is provided with an exter nal bus interface function by which external memories such as rom and ram, and i/o can be connected. 4.1 features ? address bus (capable of separate output) ? 16-bit data bus ? able to be connected to external devices via t he pins that have alter nate functions as ports ? wait function programmable wait function, capable of inserting up to 3 wait states per 2 blocks external wait control through wait input pin ? idle state insertion function ? bus hold function 4.2 bus control pins and control register 4.2.1 bus control pins the following pins are used for in terfacing with external devices. table 4-1. bus control pins external bus interface func tion corresponding port (pins) address/data bus (ad0 to ad7) port 4 (p40 to p47) address/data bus (ad8 to ad15) port 5 (p50 to p57) address bus (a1 to a4) port 11 (p110 to p113) address bus (a5 to a12) port 10 (p100 to p107) address bus (a13 to a15) port 3 (p34 to p36) address bus (a16 to a21) port 6 (p60 to p65) read/write control (lben, uben, r/w, dstb, wrl, wrh, rd) port 9 (p90 to p93) address strobe (astb) port 9 (p94) bus hold control (hldrq, hldak) port 9 (p95, p96) external wait control (wait) port 12 (p120) the bus interface function of each pin is enabled by specifying the me mory expansion mode register (mm) or the memory address output mode register (ma m). for the details of specifying an operation mode of the external bus interface, refer to 3.4.6 (1) memory expansion mode register (mm) and for (2) memory address output mode register (mam). caution for debugging using the separate bus, refer to ie-703017-mc-em1 user?s manual.
chapter 4 bus control function user?s manual u12768ej4v1ud 90 4.2.2 control register (1) system control register (syc) this register switches the c ontrol signals for bus interface. the system control register can be r ead/written in 8-bit or 1-bit units. after reset: 00h r/w address: fffff064h symbol 7 6 5 4 3 2 1 0 syc 0 0 0 0 0 0 0 bic bic bus interface control 0 dstb, r/w, lben, uben signal output 1 rd, wrl, wrh, uben note signal output note the uben signal is output regardle ss of the bic bit setting in the ex ternal expansion mode (set by the memory expansion mode register (mm)). caution when using port 9 as an i/o port, be sure to set the bic bit to 0. 4.3 bus access 4.3.1 number of access clocks the number of basic clocks necessary for accessing each resource is as follows. table 4-2. number of access clocks peripheral i/o (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) peripheral i/o (16 bits) external memory (16 bits) instruction fetch 1 3 disabled 3 + n operand data access 3 1 3 3 + n remarks 1. unit: clock/access 2. n: number of waits inserted
chapter 4 bus control function user?s manual u12768ej4v1ud 91 4.3.2 bus width the cpu carries out peripheral i/o access and external me mory access in 8-bit, 16-bit, or 32-bit units. the following shows the operation for each access. (1) byte access (8 bits) byte access is divided into two types, acce ss to even addresses and access to odd addresses. figure 4-1. byte access (8 bits) 0 7 0 7 8 15 byte data external data bus (a) access to even address 0 7 0 7 8 15 byte data external data bus (b) access to odd address (2) halfword access (16 bits) in halfword access to external memory, data is dealt with as is because the data bus is fixed to 16 bits. figure 4-2. halfword access (16 bits) 00 15 15 halfword data external data bus (3) word access (32 bits) in word access to external memory, the lower halfword is accessed fi rst and then the higher halfword is accessed. figure 4-3. word access (32 bits) 0 15 0 15 16 31 word data external data bus first 0 15 0 15 16 31 word data external data bus second
chapter 4 bus control function user?s manual u12768ej4v1ud 92 4.4 memory block function the 16 mb memory space is divided into memory blocks of 1 mb units. the progra mmable wait function and bus cycle operation mode can be i ndependently controlled for every two memory blocks. figure 4-4. memory space block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 on-chip peripheral i/o area internal ram area external memory area ffffffh f00000h efffffh e00000h dfffffh d00000h cfffffh c00000h bfffffh b00000h afffffh a00000h 9fffffh 900000h 8fffffh 800000h 7fffffh 700000h 6fffffh 600000h 5fffffh 500000h 4fffffh 400000h 3fffffh 300000h 2fffffh 200000h 1fffffh 100000h 0fffffh 000000h internal rom area
chapter 4 bus control function user?s manual u12768ej4v1ud 93 4.5 wait function 4.5.1 programmable wait function to facilitate interfacing with low-speed memories and i/o dev ices, up to 3 data waits can be inserted in a bus cycle that starts every two memory blocks. the number of waits can be pr ogrammed by using the data wa it control register (dwc). immediately after the system has been reset, a state in which three data waits are inserted is autom atically programmed for all memory blocks. (1) data wait contro l register (dwc) this register can be read/written in 16-bit units. after reset: ffffh r/w address: fffff060h symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dwc number of wait states to be inserted 0 0 0 0 1 1 1 0 2 1 1 3 n blocks into which wait states are inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom area. it is not subject to programmable wait control, regardless of the setting of dwc, and is always accessed without wait states. the internal ram area of block 15 is not subject to programmable wait control and is always accessed without wait states. the on-chip peripheral i/o area of this block is not subject to programmable wait control either; only wait control from each peri pheral function is performed. dw61 dw00 dw01 dw10 dw11 dw20 dw21 dw30 dw31 dw40 dw41 dw50 dw51 dw60 dw70 dw71 dwn0 dwn1
chapter 4 bus control function user?s manual u12768ej4v1ud 94 4.5.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (wait) to synchronize with the external device. the external wait signal is data wait only, and does not affect the access times of the internal rom, internal ram, and on-chip peripheral i/o areas, similar to programmable wait. input of the external wait signal can be done asynchronously to clkout and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle. if the setup/ hold time at sampling timing is not satisfied, the wait state may or may not be inserted in the next state. 4.5.3 relationship between progra mmable wait and external wait a wait cycle is inserted as a result of an or operation between the wait cycle specified by the set value of programmable wait and the wait cycle cont rolled by the wait pin. in other words, the number of wait cycles is determined by whichever si de has the greatest number. figure 4-5. wait control wait control programmable wait wait by wait pin for example, if the number of programmable waits and the timing of the wait pin input signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 4-6. example of inserting wait states clkout t1 t2 tw tw tw t3 wait pin wait by wait pin programmable wait wait control remark { : valid sampling timing
chapter 4 bus control function user?s manual u12768ej4v1ud 95 4.6 idle state insertion function to facilitate interfacing with low-s peed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (ti) can be inse rted into the current bus cycle after the t3 state. the following bus cycle starts after one idle state. specifying insertion of the idle st ate is programmable by using the bus cycle control register (bcc). immediately after the system has been re set, idle state insertion is automat ically programmed for all memory blocks. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. after reset: aaaah r/w address: fffff062h symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcc idle state insertion specification 0 not inserted 1 inserted n blocks into which idle state is inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom ar ea, so no idle state can be specified. the internal ram area and on-chip peripheral i/o area of blo ck 15 are not subject to inse rtion of an idle state. be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. if these bits are set to 1, the operation is not guaranteed. 0 bc01 0 bc11 0 bc21 0 bc31 0 bc41 0 bc51 0 bc61 0 bc71 bcn1
chapter 4 bus control function user?s manual u12768ej4v1ud 96 4.7 bus hold function 4.7.1 outline of function when the mm3 bit of the memory expans ion mode register (mm) is set (1), t he hldrq and hldak pin functions of p95 and p96 become valid. when the hldrq pin becomes active (low) indicating that another bus master is reques ting acquisition of the bus, the external address/data bus and str obe pins go into a high-impedance state note , and the bus is released (bus hold status). when the hldrq pin becomes inactive (high) indicating that t he request for the bus is cleared, these pins are driven again. during the bus hold per iod, the internal operation continues until the next external memory access. the bus hold status can be recognized by the hldak pin becoming active (low). this feature can be used to design a syst em where two or more bus masters ex ist, such as when a multi-processor configuration is used and when a dma controller is connected. a bus hold request is not acknowledged between the fi rst and the second word access, and between the read access and write access in a read-modify-write acce ss executed using a bit m anipulation instruction. note the a1 to a15 pins are set to the hol d state when a separ ate bus is used.
chapter 4 bus control function user?s manual u12768ej4v1ud 97 4.7.2 bus hold procedure the procedure of the bus hold f unction is illustrated below. figure 4-7. bus hold procedure hldrq hldak < 1 >< 2 >< 3 >< 4 >< 5 >< 7 >< 8 >< 9 > < 6 > <1>hldrq = 0 acknowledged <2>all bus cycle start requests held pending <3>end of current bus cycle <4>bus idle status <5>hldak = 0 <6>hldrq = 1 accepted <7>hldak = 1 <8>clears pending bus cycle start requests <9>start of bus cycle normal status bus hold status normal status 4.7.3 operation in power save mode in the idle or software stop mode, the system clock is stopped. consequently, the bus hold status is not set even if the hldrq pin becomes active. in the halt mode, the hldak pin i mmediately becomes active when the hl drq pin becomes active, and the bus hold status is set. when the hldrq pi n becomes inactive, the hldak pin becomes inactive. as a result, the bus hold status is cleared, and t he halt mode is set again.
chapter 4 bus control function user?s manual u12768ej4v1ud 98 4.8 bus timing the v850/sa1 can execute read/write control for an external device using the following two modes. ? mode using dstb, r/w, lben, uben, and astb signals ? mode using rd, wrl, wrh, and astb signals set these modes by using the bic bit of t he system control register (syc) (refer to 4.2.2 (1) system control register (syc) ). figure 4-8. memory read (1/4) (a) 0 waits t1 t2 t3 clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address data address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) h a1 to a15 (output) address remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicate s the high-impedance state.
chapter 4 bus control function user?s manual u12768ej4v1ud 99 figure 4-8. memory read (2/4) (b) 1 wait t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) t3 data h a1 to a15 (output) address remarks 1. { indicates the sampling timing when the number of programmable waits is set to 1. 2. the broken line indicate s the high-impedance state.
chapter 4 bus control function user?s manual u12768ej4v1ud 100 figure 4-8. memory read (3/4) (c) 0 waits, idle state t1 t2 t3 clkout (output) a1 to a15 (output) ad0 to ad15 (i/o) address address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) h ti data a16 to a21 (output) address remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicate s the high-impedance state.
chapter 4 bus control function user?s manual u12768ej4v1ud 101 figure 4-8. memory read (4/4) (d) 1 wait, idle state clkout (output) a1 to a15 (output) ad0 to ad15 (i/o) address address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) a16 to a21 (output) address t1 t2 tw t3 ti h data remarks 1. { indicates the sampling timing when the number of programmable waits is set to 1. 2. the broken line indicate s the high-impedance state.
chapter 4 bus control function user?s manual u12768ej4v1ud 102 figure 4-9. memory write (1/2) (a) 0 waits clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) rd (output) wrh, wrl (output) a1 to a15 (output) address t1 t2 t3 h data note note ad0 to ad7 output invalid data w hen odd-address byte data is accessed. ad8 to ad15 output invalid data when even-address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state.
chapter 4 bus control function user?s manual u12768ej4v1ud 103 figure 4-9. memory write (2/2) (b) 1 wait t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) rd (output) wrh, wrl (output) t3 data note address h a1 to a15 (output) address note ad0 to ad7 output invalid data w hen odd-address byte data is accessed. ad8 to ad15 output invalid data when even-address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 1. 2. the broken line indicates the high-impedance state.
chapter 4 bus control function user?s manual u12768ej4v1ud 104 figure 4-10. bus hold timing clkout (output) r/w (output) dstb, rd, wrh, wrl (output) uben, lben (output) wait (input) hldrq (input) hldak (output) a16 to a21 (output) a1 to a15 (output) ad0 to ad15 (i/o) address address address address address astb (output) undefined address note 1 note 2 t2 t1 t3 th th th th ti t1 data notes 1. if the hldrq signal is inactive (high level) at th is sampling timing, the bus hold state is not entered. 2. if the bus hold status is entered after a write cycle, a high level ma y be output momentarily from the r/w pin immediately before the hldak signal changes from high level to low level. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicate s the high-impedance state.
chapter 4 bus control function user?s manual u12768ej4v1ud 105 4.9 bus priority there are four external bus cycles: bus hold, memory access, instruction fetch (branch), and instruction fetch (continuous). the bus hold cycle is given the highest priority, followed by memory access, instruction fetch (branch), and instruction fetch (cont inuous) in that order. the instruction fetch cycle may be in serted between the read access and writ e access in a read-modify-write access. no instruction fetch cycle is inserted between the lo wer halfword access and higher halfword access of word access operations. table 4-3. bus priority external bus cycle priority bus hold 1 memory access 2 instruction fetch (branch) 3 instruction fetch (continuous) 4 4.10 memory boundary operation conditions 4.10.1 program space (1) do not execute a branch to the on- chip peripheral i/o area or continuous fe tch from the internal ram area to peripheral i/o area. if a branch or instruction fetch is executed, the nop instructi on code is continuously fetched and no data is fetched from external memory. (2) a prefetch operation stradd ling over the on-chip peripheral i/o area (inva lid fetch) does not take place if a branch instruction exists at the upper-limit address of the internal ram area. 4.10.2 data space only the address aligned at the halfw ord boundary (when the least significant bit of the address is ?0?)/word boundary (when the lowest 2 bits of the address are ?0?) is accessed by halfwor d (16 bits)/word (32 bits) data. therefore, access that straddles over the memory or memory block boundary does not take place. for details, refer to v850 series architecture user?s manual .
user?s manual u12768ej4v1ud 106 chapter 5 interrupt/exception processing function 5.1 outline the v850/sa1 is provided with a dedicat ed interrupt controller (intc) for in terrupt servicing and realizes a high- powered interrupt function that can service inte rrupt requests from a total of 30 sources. an interrupt is an event that occu rs independently of program execution, and an excepti on is an event that is dependent on program execution. the v850/sa1 can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (fetching of an illegal opcode) (exception trap). 5.1.1 features ? interrupts external interrupts: 8 sources (5 sources note ) internal interrupts: 24 sources 8 levels of programmable priorities mask specification for interrupt requests according to priority masks can be specified for each maskable interrupt request. noise elimination, edge detection, and valid edge of external interrupt request signal can be specified. note number of external interrupts t hat can release the software stop mode. ? exceptions software exceptions: 32 sources exception trap: 1 source (illegal opcode exception) the interrupt/exception sources are listed in table 5-1.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 107 table 5-1. interrupt source list (1/2) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset interrupt ? reset reset input ? 0000h 00000000h u ndefined ? interrupt ? nmi nmi pin input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt wdtovf non-maskable wdt 0020h 00000020h nextpc ? exception ? trap0n trap instruction ? 004nh note 1 00000040h nextpc ? software exception exception ? trap1n trap instruction ? 005nh note 1 00000050h nextpc ? exception trap exception ? ilgop illegal opcode ? 0060h 00000060h nextpc ? 0 intwdtm wdtovf maskable wdt 0080h 00000080h nextpc wdtic 1 intp0 intp0 pin pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin pin 00f0h 000000f0h nextpc pic6 8 intwti watch timer prescaler wt 0100h 00000100h nextpc wtiic 9 inttm00 inttm00 tm0 0110h 00000110h nextpc tmic00 10 inttm01 inttm01 tm0 0120h 00000120h nextpc tmic01 11 inttm10 inttm10 tm1 0130h 00000130h nextpc tmic10 12 inttm11 inttm11 tm1 0140h 00000140h nextpc tmic11 13 inttm2 tm2 compare match/ovf tm2 0150h 00000150h nextpc tmic2 14 inttm3 tm3 compare match/ovf tm3 0160h 00000160h nextpc tmic3 15 inttm4 tm4 compare match/ovf tm4 0170h 00000170h nextpc tmic4 16 inttm5 tm5 compare match/ovf tm5 0180h 00000180h nextpc tmic5 17 intiic0 note 2 / intcsi0 i 2 c interrupt/ csi0 transmit end i 2 c/ csi0 0190h 00000190h nextpc csic0 18 intser0 uart0 serial error uart0 01a0h 000001a0h nextpc seric0 19 intsr0/ intcsi1 uart0 receive end/ csi1 transmit end uart0/ csi1 01b0h 000001b0h nextpc csic1 20 intst0 uart0 transmit end uart0 01c0h 000001c0h nextpc stic0 maskable interrupt 21 intcsi2 csi2 transmit end csi2 01d0h 000001d0h nextpc csic2 notes 1. n: 0 to fh 2. available only in the pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by and 70f3017ay.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 108 table 5-1. interrupt source list (2/2) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register 22 intser1 uart1 serial error uart1 01e0h 000001e0h nextpc seric1 23 intsr1 uart1 receive end uart1 01f0h 000001f0h nextpc sric3 24 intst1 uart1 transmit end uart1 0200h 00000200h nextpc stic1 25 intad a/d conversion end a/d 0210h 00000210h nextpc adic 26 intdma0 dma0 transfer end dma0 0220h 00000220h nextpc dmaic0 27 intdma1 dma1 transfer end dma1 0230h 00000230h nextpc dmaic1 28 intdma2 dma2 transfer end dma2 0240h 00000240h nextpc dmaic2 maskable interrupt 29 intwt watch timer ovf wt 0250h 00000250h nextpc wtic remarks 1. default priority: priority when two or more maskabl e interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to ei pc or fepc when interrupt/exception processing is started. however, the va lue of the pc saved when an interrupt is acknowledged during divh (division) instru ction execution is the value of the pc of the current instruction (divh). 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). 3. the restored pc of an interrup t/exception other than reset is t he value of the pc (when an event occurred) + 1. 4. the non-maskable interrupt (intwdt) and maskabl e interrupt (intwdtm) are set by the wdtm4 bit of the watchdog timer mode register (wdtm).
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 109 5.2 non-maskable interrupts non-maskable interrupt requests are acknowledged unconditionally , even in the interrupt disabled (di) status. nmi requests are not subject to priority control and take precedence over all the other interrupts. the v850/sa1 includes the following two non-maskable interrupt requests. nmi pin input (nmi) non-maskable watchdog timer interrupt request (intwdt) when the valid edge specified by rising edge specification register 0 (egp0) and falling edge s pecification register 0 (egn0) is detected at the nmi pin, an interrupt occurs. intwdt functions as the non-maskable interrupt (intwdt) only in the stat e in which the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 1. while the service routine of a non-ma skable interrupt is being executed ( psw.np = 1), the acknowledgement of another non-maskable interrupt request is held pending. the pending nmi is acknowledged when psw.np is cleared to 0 after the original service routine of the non-mask able interrupt under execution has been terminated (by the reti instruction). note that if two or mo re nmi requests are input during the execut ion of the service routine for an nmi, the number of nmis that will be acknowledged a fter psw.np goes to ??0??, is only one. caution do not clear psw.np to 0 by the ldsr inst ruction during non-maskable interrupt servicing. if psw.np is cleared to 0, the interrupts a fterwards cannot be acknowledged correctly.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 110 5.2.1 operation if a non-maskable interrupt request is generated, the cpu performs the followi ng processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception codes (0010h, 0020h) to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> loads the handler address (00000010h, 00000020h) of the non-maskable interrupt routine to the pc, and transfers control. figure 5-1. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address intc acknowledged cpu processing psw. np 1 0 handler address: 00000010h (nmi) 00000020h (intwdt)
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 111 figure 5-2. acknowledging non -maskable interrupt request (a) if a new nmi request is generated while an nmi ser vice routine is being executed main routine nmi request nmi request (psw. np = 1) nmi request held pending because psw. np = 1 pending nmi request processed (b) if a new nmi request is generated twice while an nmi service routine is being executed main routine nmi request nmi request held pending because nmi service program is being processed held pending because nmi service program is being processed nmi request only one nmi request is acknowledged even though two or more nmi requests are generated
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 112 5.2.2 restore execution is restored from non-maskable interr upt servicing by the reti instruction. operation of reti instruction when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. (1) restores the values of the pc and psw from fepc and fepsw, respecti vely, because the ep bit of psw is 0 and the np bit of psw is 1. (2) transfers control back to the address of the restored pc and psw. the following illustrates how the reti instruction is processed. figure 5-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and psw.np bit ar e changed by the ldsr instruction during non- maskable interrupt servicing, in order to restor e the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 113 5.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt (nmi ) servicing is under execution. this flag is set when an nmi interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged. figure 5-4. np flag (np) after reset: 00000020h symbol 31 8 7 6 5 4 3 2 1 0 psw 0 np ep id sat cy ov s z np nmi servicing state 0 no nmi interrupt servicing 1 nmi interrupt currently being serviced 5.2.4 noise elimination of external interrupt request input pin (1) noise elimination of nm i and intp0 to intp3 pins the noise of the nmi pin and intp0 to intp3 pins is eliminated by the noise elim inator using analog delay. therefore, signals input to the nmi and intp0 to intp3 pins are not detec ted as an edge, unless they maintain their input level for a certain period. the edge is detected after a certain period has elapsed. the nmi and intp0 to intp3 pins can be used for releas ing the software stop mode. in the software stop mode, the system clock is not used for noise elimi nation because the internal system clock is stopped. (2) noise elimination of intp4 to intp6 pins the intp4 to intp6 pins incorporate a digital noise elimi nator. if the input level of the intp pin is detected by the sampling clock (f xx ) and the same level is not detected three succe ssive times, the input pulse is eliminated as a noise. in the software stop mode, the intp4 to intp6 pins cannot be used for releasing the software stop mode because the internal system cl ock is stopped. note the following. if the input pulse width is between 2 and 3 clocks, w hether the input pulse is detected as a valid edge or eliminated as noise is undefined. to securely detect the level as a valid edge, the same level input of 3 clocks or more is required. when noise is generated in synchronization with the samp ling clock, this may not be recognized as noise. in this case, eliminate the noise by adding a filter to the input pin.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 114 5.2.5 edge detection function of ext ernal interrupt request input pin the nmi pin valid edge can be selected from the follo wing four types: falling edge, rising edge, both edges, or neither edge. rsing edge specification regist er 0 (egp0) and falling edge specification r egister 0 (egn0) specify the valid edge of the external interrupt. these two register s can be read/written in 1-bit or 8-bit units. after reset, the valid edge of the external interrupt request input pin is set to the ?det ect neither rising nor falling edge? state. therefor e, the nmi pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by us ing the egp0 and egn0 registers. when using the p00 pin as an output port, set the nmi pin valid edge to ?detect neither rising nor falling edge?. when using the p01 to p07 pins as an out put port, set the valid edges of the intp 0 to intp6 pins to ?detect neither rising nor falling edge? or mask the interrupt requests. (1) rising edge specification register 0 (egp0) after reset: 00h r/w address: fffff0c0h symbol 7 6 5 4 3 2 1 0 egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n rising edge valid control 0 no interrupt request signal occurred at the rising edge 1 interrupt request signal occurred at the rising edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pin control (2) falling edge specification register 0 (egn0) after reset: 00h r/w address: fffff0c2h symbol 7 6 5 4 3 2 1 0 egn0 egn07 egn06 egn05 eg n04 egn03 egn02 egn01 egn00 egn0n falling edge valid control 0 no interrupt request signal occurred at the falling edge 1 interrupt request signal occurred at the falling edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pin control
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 115 5.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. t he v850/sa1 has 30 maskable interrupt sources (refer to 5.1.1 features ). if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight le vels of priorities can be spec ified by using the interrupt control registers, allowing progr ammable priority control. when an interrupt request has been ackno wledged, the acknowledgement of other maskable interrupts is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt servici ng routine, the interrupt enabled (ei) status is set which enables interrupts having a higher priority to immediately interr upt the current service routi ne in progress. note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to use multiple interrupts, it is necessary to save eipc and eipsw to memory or a regi ster before exec uting the ei instruction, and restore eipc and eipsw to the original values by executi ng the di instructi on before the reti instruction. when the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 0, the watchdog timer overflow interrupt functions as a ma skable interrupt (intwdtm). 5.3.1 operation if a maskable interrupt occurs by int input, the cpu perfo rms the following processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to t he lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> loads the corresponding handler address to the pc, and transfers control. the int input masked by intc and the int input that occurs during the ot her interrupt servicing (when psw.np = 1 or psw.id = 1) are internally held pending. when t he interrupts are unmasked, or when psw.np = 0 and psw.id = 0 by using the reti and ldsr instructions, the pending int is input to start the new maskable interrupt servicing. how the maskable interrupts are serviced is shown below.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 116 figure 5-5. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id pc intc acknowledged cpu processing mask? yes no psw. id = 0 priority higher than that of interrupt currently serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? interrupt enable mode? restored pc psw exception code 0 1 handler address
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 117 5.3.2 restore to restore execution from maskable interrupt servicing, the reti instruction is used. operation of reti instruction when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. (1) restores the values of the pc and psw from ei pc and eipsw because the ep bi t of the psw is 0 and the np bit of the psw is 0. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 5-6. reti instruction processing reti instruction original processing restored pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 118 5.3.3 priorities of maskable interrupts the v850/sa1 provides multiple interr upt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts c an be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels which are s pecified by the interrupt priority level specification bit (xxprn). when two or more interrupts having the same priority level specifi ed by xxprn are generated at t he same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, refer to table 5-1 interrupt source list . programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is a cknowledged, the id flag of the psw is aut omatically set to ??1??. therefore, when multiple interrupts are to be used, clear the id flag to ??0?? beforehand (for example, by placing the ei instruction into the interrupt servicing progra m) to set the interrupt enabled mode. remark xx: identification name of each peripheral unit (refer to table 5-2 ) n: number of each peripheral unit (refer to table 5-2 )
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 119 figure 5-7. example of multip le interrupt se rvicing (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interr upt requests shown for t he sake of explanation. 2. the default priority in the above figure indicates t he relative priority between two interrupt requests.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 120 figure 5-7. example of multip le interrupt se rvicing (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has a higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has a higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 121 figure 5-8. example of servicing interr upt requests generate d simultaneously main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b servicing of interrupt request c servicing of interrupt request a interrupt requests b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has a higher default priority. notes 1. higher default priority 2. lower default priority remarks 1. a, b, and c in the above figure are the names of interrupt r equests shown for the sake of explanation. 2. the default priority in the above figure indicates t he relative priority between two interrupt requests.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 122 5.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each mask able interrupt and sets the control conditions for each maskable interrupt request. the interr upt control register can be read/wr itten in 8-bit or 1-bit units. cautions 1. if the following three conditions conflict, interrupt servici ng will be performed twice. however, interrupt servicing is not performed twice if dma is not being used. ? execution of bit manipulation instructi on for interrupt request flag (xxifn) ? interrupt request generated by the same hardware interrupt c ontrol register (xxicn) as the interrupt request flag (xxifn) ? dma activated during execution of bit manipulat ion instruction for interrupt request flag (xxifn) two software-based counte rmeasures are shown below. { insert the di and ei instructions before and after (respectivel y) the software bit manipulation instruction to avoid jumping to an interrupt immediately after execution of the bit manipulation instruction. { because interrupts are disabled (di state) by ha rdware after an interr upt request has been acknowledged, clear the interrupt request flag (xxifn) before executing the ei instruction in each interrupt servicing routine. 2. read the xxifn bit of the xxi cn register with interrupts disable d. when the xxifn bit is read with interrupts enabled, a normal value may not be read if the interrupt acknowledgement timing and the bit reading timing conflict.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 123 after reset: 47h r/w address: fffff100h to fffff13ah symbol 7 6 5 4 3 2 1 0 xxicn xxifn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 xxifn interrupt request flag note 0 interrupt request not generated 1 interrupt request generated xxmkn interrupt mask flag 0 interrupt servicing enabled 1 interrupt servicing disabled (pending) xxprn2 xxprn1 xxprn0 interrupt pr iority specification bit 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest) note automatically reset by hardware when an interrupt request is acknowledged. remark xx: identification name of each peripheral unit (refer to table 5-2 ) n: number of each peripheral unit (refer to table 5-2 ) the address and bits of each interrupt control register are as follows.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 124 table 5-2. interrupt control register (xxicn) bit address register 7 6 5 4 3 2 1 0 fffff100h wdtic wdtif wdtmk 0 0 0 wdtpr2 wdtpr1 wdtpr0 fffff102h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff104h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff106h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff108h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff10ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff10ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff10eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff110h wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff112h tmic00 tmif00 tmmk00 0 0 0 tmpr002 tmpr001 tmpr000 fffff114h tmic01 tmif01 tmmk01 0 0 0 tmpr012 tmpr011 tmpr010 fffff116h tmic10 tmif10 tmmk10 0 0 0 tmpr102 tmpr101 tmpr100 fffff118h tmic11 tmif11 tmmk11 0 0 0 tmpr112 tmpr111 tmpr110 fffff11ah tmic2 tmif2 tmmk2 0 0 0 tmpr22 tmpr21 tmpr20 fffff11ch tmic3 tmif3 tmmk3 0 0 0 tmpr32 tmpr31 tmpr30 fffff11eh tmic4 tmif4 tmmk4 0 0 0 tmpr42 tmpr41 tmpr40 fffff120h tmic5 tmif5 tmmk5 0 0 0 tmpr52 tmpr51 tmpr50 fffff122h csic0 csif0 csmk0 0 0 0 cspr02 cspr01 cspr00 fffff124h seric0 serif0 sermk0 0 0 0 serpr02 serpr01 serpr00 fffff126h csic1 csif1 csmk1 0 0 0 cspr12 cspr11 cspr10 fffff128h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff12ah csic2 csif2 csmk2 0 0 0 cspr22 cspr21 cspr20 fffff12ch seric1 serif1 sermk1 0 0 0 serpr12 serpr11 serpr10 fffff12eh sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff130h stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff132h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff134h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff136h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff138h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff13ah wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 125 5.3.5 in-service priori ty register (ispr) this register holds the priority leve l of the maskable interrupt currently a cknowledged. when an interrupt request is acknowledged, the bit of this register co rresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the inte rrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset when executi on is returned from non-maskable interrupt processing or exception processing. this register is read-only in 8-bit or 1-bit units. caution read the ispr register with interrupts disabled. when the ispr register is read with interrupts enabled, a normal value may not be read if the interrupt acknowledgeme nt timing and the bit reading timing conflict. after reset: 00h r address: fffff166h symbol 7 6 5 4 3 2 1 0 ispr ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 isprn indicates priority of interrupt currently acknowledged 0 interrupt request with priority n not acknowledged 1 interrupt request with priority n acknowledged remark n: 0 to 7 (priority level)
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 126 5.3.6 id flag the interrupt disable status flag (id) of the psw controls the enabling and disabling of maskable interrupt requests. as a status flag, it also displays the curr ent maskable interrupt acknowledgment status. figure 5-9. interrupt disable flag (id) after reset: 00000020h symbol 31 8 7 6 5 4 3 2 1 0 psw 0 np ep id sat cy ov s z id maskable interrupt se rvicing specification note 0 maskable interrupt request acknowledgement enabled 1 maskable interrupt reques t acknowledgement disabled note interrupt disable flag (id) function it is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr inst ruction when referencing the psw. non-maskable interrupt requests and exceptions are acknowledged regardless of this flag. when a maskable interrupt request is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during the acknowledgement dis abled period (id = 1) can be acknowledged when the xxifn bit of xxicn is se t to 1, and the id flag is reset to 0. remark xx: identification name of each peripheral unit (refer to table 5-2 ) n: number of each peripheral unit (refer to table 5-2 ) 5.3.7 watchdog timer mode register (wdtm) this register can be read/written in 8-bi t or 1-bit units (for details, refer to chapter 9 watchdog timer ). after reset: 00h r/w address: fffff384h symbol 7 6 5 4 3 2 1 0 wdtm run 0 0 wdtm4 0 0 0 0 run watchdog timer operation control 0 count operation stopped 1 count start after clearing wdtm4 timer mode selection/interrupt control by wdt 0 interval timer mode 1 wdt mode caution if the run or wdtm4 bit is set to 1, it cannot be cleared other than by reset input.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 127 5.4 software exceptions a software exception is generated when the cpu ex ecutes the trap instru ction, and can be always acknowledged. trap instruction format: trap vector (where vector is 0 to 1fh) for details of the instruct ion function, refer to the v850 series architecture user?s manual. 5.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of psw. (5) loads the handler address (00000040h or 00000050h) of the software exception routine in the pc, and transfers control. how a software exception is processed is shown below. figure 5-10. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing handler address: 00000040h (vector = 0nh) 00000050h (vector = 1nh)
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 128 5.4.2 restore to restore or return execution from the software except ion service routine, the re ti instruction is used. operation of reti instruction when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 5-11. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception process, in orde r to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 129 5.4.3 ep flag the ep flag in the psw is a status flag used to indicate t hat exception processing is in progress. it is set when an exception occurs. figure 5-12. ep flag (ep) after reset: 00000020h symbol 31 8 7 6 5 4 3 2 1 0 psw 0 np ep id sat cy ov s z ep exception processing 0 exception processing is not in progress 1 exception processing is in progress 5.5 exception trap the exception trap is an interr upt that is requested when ill egal execution of an instruct ion takes place. in the v850/sa1, an illegal opcode exception (ilgop: illegal op code trap) is considered as an exception trap. illegal opcode exception: o ccurs if the sub opcode field of the instruction to be ex ecuted next is not a valid opcode. 5.5.1 illegal opcode definition an illegal opcode is defined to be a 32-bit word with bi ts 5 to 10 being 111111b and bits 23 to 26 being 0011b to 1111b. figure 5-13. illegal opcode 15 16 17 23 22 x 21 x 20 xxxxx x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 12 13 1 1 1 1 0 to 1 0 1 x: don?t care
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 130 5.5.2 operation if an exception trap occurs, the cpu performs the following pr ocessing, and transfers contro l to the handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code (0060h) to the lower 16 bits (eicc) of ecr. (4) sets the ep and id bits of the psw. (5) loads the handler address (00000060h) for the excepti on trap routine to the pc, and transfers control. how the exception trap is processed is shown below. figure 5-14. exception trap processing exception trap (ilgop) occurs eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 00000060h cpu processing exception processing
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 131 5.5.3 restore to restore or return execution from the exc eption trap, the reti in struction is used. operation of reti instruction when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 5-15. reti instruction processing reti instruction jump to pc pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep and the psw.np bit are changed by the ldsr instruction during the exception trap process, in order to restore the pc and psw correctly during recovery by the reti instruction, it is n ecessary to set psw.ep back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 132 5.6 priority control 5.6.1 priorities of interrupts and exceptions table 5-3. priorities of interrupts and exceptions reset nmi int trap ilgop reset * * * * nmi int trap ilgop reset: reset nmi: non-maskable interrupt int: maskable interrupt trap: software exception ilgop: illegal opcode exception *: the item on the left ignores the item above. : the item on the left is i gnored by the item above. : the item above is higher than t he item on the left in priority. : the item on the left is higher t han the item above in priority. 5.6.2 multiple interrupts multiple interrupt servicing is a func tion that allows the nesting of interrupt s. if a higher priority interrupt is generated and acknowledged, it will be allowed to stop a current interrupt servicing r outine in progress. execution of the original routine will resume once the higher priority interrupt routine is completed. if an interrupt with a lower or equal prio rity is generated and a service routine is currently in progress, the later interrupt will be held pending. multiple interrupt servicing control is performed when in the interrupt enabled state (id = 0). even in an interrupt servicing routine, the interrupt enabled state (id = 0) must be set. if a maskable interrupts are enabled or an exception is gener ated during a service program of a maskable interrupt or exception, eipc and eipsw must be saved. the following example shows the procedure of interrupt nesting.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 133 (1) to acknowledge maskable in terrupts in service program service program of maskable interrupt or exception (2) to generate excepti on in service program service program of maskable interrupt or exception priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt servicing control. to set a priority level, write values to the xxprn0 to xxp rn2 bits of the interrupt request control register (xxicn) corresponding to each maskable interrupt r equest. at reset, the interrupt request is masked by the xxmkn bit, and the priority level is set to 7 by the xxprn0 to xxprn2 bits. remark xx: identification name of each peripheral unit (refer to table 5-2 ) n: number of each peripheral unit (refer to table 5-2 ) ... ... save eipc to memory or register save eipsw to memory or register ei instruction (enables interrupt acknowledgement) ... ... di instruction (disables interrupt acknowledgement) restore saved value to eipsw restore saved value to eipc reti instruction ... ... save eipc to memory or register save eipsw to memory or register ei instruction (enables interrupt acknowledgement) ... trap instruction illegal opcode ... restore saved value to eipsw restore saved value to eipc reti instruction acknowledgement of interrupt such as intp input. acknowledgement of exception such as trap instruction. acknowledgement of exception such as illegal opcode.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 134 priorities of maskable interrupts (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspended as a result of multiple interrupt serv icing is resumed after the interrupt servicing of the higher priority has been comple ted and the reti instruct ion has been executed. a pending interrupt request is acknowledged after the current interrupt servicing has been completed and the reti instruction has been executed. caution in the non-maskable interrupt servicing rout ine (time until the reti instruction is executed), maskable interrupts are not ack nowledged but are suspended.
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 135 5.7 interrupt latency time the following table describes the v850/ sa1 interrupt latency time (from in terrupt request generation to start of interrupt servicing). figure 5-16. pipeline operation at interrupt request acknowledgement system clock if id ifx idx ifx ex mem int1 int2 int3 if id ex mem wb int4 wb interrupt request instruction 1 instruction 2 instruction 3 interrupt acknowledgement operation instruction (start instruction of interrupt servicing routine) 7 to 14 system clocks 4 system clocks int1 to int4: interrupt acknowledgement processing if x : invalid instruction fetch id x : invalid instruction decode interrupt latency time (system clock) internal interrupt external interrupt condition minimum 11 13 maximum 18 20 time to eliminate noise (2 system clocks) is also necessary for external interrupts, except when: in idle/software stop mode external bus is accessed two or more interrupt request non-sample instructions are executed in succession an interrupt control register is accessed 5.8 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample in struction and the next instruction. interrupt request non-sample instructions ei instruction di instruction ldsr reg2, 0x5 instruction (vs. psw)
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 136 5.8.1 interrupt request valid timing after ei instruction when an interrupt request signal is generated (if flag = 1) in the status in which the di instruction is executed (interrupts disabled) and interrupts are not masked (mk flag = 0), seven system cl ocks are required from the execution of the ei instruction (int errupts enabled) to the interrupt request ack nowledgement by the cpu. the cpu does not acknowledge interrupt requests if the di instruction (interrupts disabled) is executed during the seven system clocks. therefore, seven system clo cks worth of instruction execution clocks mu st be inserted after the ei instruction (interrupts enabled). however, under the following conditi ons, interrupt requests cannot be acknowledged even if the seven system clocks are secured, so securing under the following conditions is prohibited. ? in idle/software stop mode ? an interrupt request non-sampling instruction (instr uction to manipulate the psw.id bit) is executed ? an interrupt request control register (xxicn) is accessed the following shows an exampl e of program processing. [program processing example] di : ; (mk flag = 0) : ; interrupt request occurs (if flag = 1) ei ; ei instruction executed nop ; 1 system clock nop ; 1 system clock nop ; 1 system clock nop ; 1 system clock jr lp1 ; 3 system clocks (branch to lp1 routine) : lp1 : ; lpi routine di ; after ei instruction execution, nop instruction is executed four times, and di instruction is executed at the eighth clock by jr instruction note do not execute the di instructi on (psw.id = 1) during this period. remarks 1. in this example, the di instructi on is executed at the eighth clock afte r execution of the ei instruction, so the cpu acknowledges an interrupt reques t signal and performs interrupt servicing. 2. the interrupt servicing routine instructions are not executed at the eighth clock after the ei instruction execution. the inte rrupt servicing routine instructi ons are executed the four system clocks after the cpu acknowledges the interrupt request signal. 3. this example shows the case in which an inte rrupt request signal is gener ated (if flag = 1) before the ei instruction is ex ecuted. if an interrupt request signal is generated after the ei instruction is executed, the cpu does not ack nowledge the interrupt request signal if interrupts are disabled (psw.id = 1) for seven clocks a fter the if flag is set (1). note
chapter 5 interrupt/exception processing function user?s manual u12768ej4v1ud 137 figure 5-17. pipeline flow and inte rrupt request signal generation timing if id if id if id if id if id if id if id if id if id ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ei nop nop nop nop nop nop nop di if id if id if id if id if id if id if id if id ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ei nop nop nop nop nop nop di (a) when di instruction is executed at eighth clock after ei instruction execution (interrupt request is acknowledged) (b) when di instruction is executed at seventh clock after ei instruction execution (interrupt request is not acknowledged) ei signal intrq signal ei signal intrq signal intrq signal is generated intrq signal is not generated 5.9 interrupt control register bit manipul ation instructions during dma transfer to manipulate the bits of the interrupt control register ( xxicn) in the ei state when us ing the dma function, execute the di instruction before manipulation and ei instruction afte r manipulation. alternatively, clear (0) the xxif bit at the start of the interrupt servicing routine. when not using the dma function, thes e manipulations are not necessary. remark xx: peripheral unit identification name (see table 5-2 ) n: peripheral unit number (see table 5-2 )
user?s manual u12768ej4v1ud 138 chapter 6 clock generation function 6.1 general the clock generator is a circuit that generates the clock pulses that ar e supplied to the cpu and peripheral hardware. there are two types of clock oscillators. (1) main clock oscillator this oscillator has an oscillation frequency of 2 to 20 mhz. oscillation can be stopped by setting the software stop mode or by setting the processor clock control r egister (pcc). oscillation is also stopped during a reset. external clocks can be directly input. at this time, i nput a clock signal only to the x1 pin and leave the x2 pin open. cautions 1. when the main cl ock oscillator is stopped by inputti ng a reset or setting the software stop mode, the oscillation stabilization time is secured after the stop mode is released. this oscillation stabilization time is set vi a the oscillation stabilization time select register (osts). the watchdog timer is u sed as the timer that counts the oscillation stabilization time. 2. if stoppage of the main cl ock is released by clearing mck to 0 after the main clock is stopped by setting the mck bit in the pcc regist er to 1, the oscillation stabilization time is not secured. (2) subclock oscillator this circuit has an oscillation frequency of 32.768 khz. its oscillation is not stopped when the software stop mode is set, neither is it stopped when a reset is i nput. to stop oscillation, connect the xt1 pin to v ss . external clocks can be directly input. at this time, input a clock signal to the xt1 pin and input its inverted signal to the xt2 pin.
chapter 6 clock generation function user?s manual u12768ej4v1ud 139 6.2 configuration figure 6-1. clock generator prescaler idle control halt control prescaler xt1/p114 xt2 x1 x2 clkout f xt f xx f xx /2 f xx /4 f xx /8 f xt halt mfrc ck2 to ck0 clock supplied to watch timer, etc. cpu clock (f cpu ) clock supplied to peripheral hardware idle stp, mck subclock oscillator main clock oscillator selector idle control remark f xx : main clock frequency f xt : subclock frequency 6.3 clock output function this function outputs the cpu clock via the clkout pin. when clock output is enabled, the cpu clo ck is output via the clkout pin. w hen it is disabled, a low-level signal is output via the clkout pin. output is stopped in the idle or softw are stop mode (fixed to low level). this function is controlled via the dclk1 and dclk0 bits in the psc register. the high-impedance status is set during the reset period. after reset is released, a low level is output. caution while clkout is being output , do not change the cpu clock (ck2 to ck0 bits of pcc register).
chapter 6 clock generation function user?s manual u12768ej4v1ud 140 6.3.1 control registers (1) processor clock control register (pcc) this is a specific register. it can be written to onl y when a specified combinati on of sequences is used (see 3.4.9 specific registers ). this register can be read/written in 8-bit or 1-bit units. after reset: 03h r/w address: fffff074h 7 6 5 4 3 2 1 0 pcc 0 mck mfrc 0 0 ck2 ck1 ck0 mck operation of main clock 0 operating 1 stopped mfrc selection of internal f eedback resistor for main clock 0 use 1 do not use ck2 note1, 2 ck1 ck0 selection of cpu clock 0 0 0 f xx 0 0 1 f xx /2 0 1 0 f xx /4 0 1 1 f xx /8 1 x x f xt (subclock) notes 1. if manipulating ck2, do so in 1-bit units. in the case of 8-bit mani pulation, do not change the values of ck1 and ck0. 2. when the cpu operates on the subclock (ck2 = 1), do not set the software stop mode. cautions 1. while clkout is being output, do not change the cpu cl ock (the value of the ck2 to ck0 in the pcc register). 2. even if the mck bit is set to 1 during main clock operation, th e main clock is not stopped. the cpu clock stops after the subclock is selected. 3. always set bits 3, 4, and 7 to 0. 4. leakage current can be re duced by avoiding the use of the main clock?s on-chip feedback resistor (mfrc = 1) while the ext ernal clock is operating. however, the leakage current cannot be reduced duri ng the oscillation stabilization time,. remark x: don?t care
chapter 6 clock generation function user?s manual u12768ej4v1ud 141 (a) example of main clock operation subclock operation setup <1> ck2 1: bit manipulation instructions ar e recommended. do not change ck1 and ck0. <2> subclock operation: the maximu m number of the following instruct ions is required before subclock operation after the ck2 bit is set. (cpu clock frequency before setting/subclock frequency) 2 therefore, insert the wait described above using a program. <3> mck 1: only when the main clock is stopped. (b) example of subclock operation main clock operation setup <1> mck 0: main clock oscillation start <2> insert a wait using a program and wait until t he main clock oscillation stabilization time elapses. <3> ck2 0: bit manipulation instructions ar e recommended. do not change ck1 and ck0. <4> main clock operation: at least two instructions are required before main cl ock operation after the ck2 bit is set.
chapter 6 clock generation function user?s manual u12768ej4v1ud 142 (2) power save control register (psc) this is a specific register. it can be written to onl y when a specified combinati on of sequences is used (see 3.4.9 specific registers ). this register can be read/written in 8-bit or 1-bit units. after reset: c0h r/w address: fffff070h 7 6 5 4 3 2 1 0 psc dclk1 dclk0 0 0 0 idle stp 0 dclk1 dclk0 specification of cl kout pin operation 0 0 output enabled 0 1 setting prohibited 1 0 setting prohibited 1 1 output disabled (when reset) idle idle mode setting 0 normal mode 1 idle mode note 1 stp software stop mode setting 0 normal mode 1 software stop mode notes 2, 3 notes 1. when idle mode is released, this bit is automatically reset to 0. 2. when software stop mode is released, this bit is automatically reset to 0. 3. when the cpu operates on the subclock (ck2 = 1), do not set the stp bit to 1. cautions 1. the dclk0 and dclk1 bits should be manipulated in 8-bit units. 2. do not set (1) the idle bit and stp bi t at the same time. if they are set simultaneously, the software stop mode is entered. 3. be sure to set bits 3 to 5 to 0.
chapter 6 clock generation function user?s manual u12768ej4v1ud 143 (3) oscillation stabilization time select register (osts) this register can be read/written in 8-bit units. after reset: 04h r/w address: fffff380h 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time note 0 0 0 2 14 /f xx (819.2 s) 0 0 1 2 16 /f xx (3.3 ms) 0 1 0 2 17 /f xx (6.6 ms) 0 1 1 2 18 /f xx (13.1 ms) 1 0 0 2 19 /f xx (26.2 ms) other than above setting prohibited note the numerical value in par entheses is the value when f xx = 20 mhz. 6.4 power save functions 6.4.1 general this product provides the following power saving functions. these modes can be combined and switched to suit the target application, wh ich enables effective implementation of low-power systems. (1) halt mode when in this mode, the clock?s oscillator continues to operate but the cpu?s operating clock is stopped. a clock continues to be supplied for other on-ch ip peripheral functions to maintain operation of those functions. this enables the system?s total power consumption to be reduced. a dedicated instruction (the ha lt instruction) is used to switch to halt mode. (2) idle mode this mode stops the entire system by stopping the cpu?s operating clock as well as the operating clock for on- chip peripheral functions other than for the watch timer while the clock oscilla tor is still operating. however, the subclock continues to operate and supplies a cl ock to the on-chip peripheral functions. when this mode is released, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. when the idle bit of the power save control register (psc) is set to 1, the system switches to idle mode.
chapter 6 clock generation function user?s manual u12768ej4v1ud 144 (3) software stop mode this mode stops the entire system by stopping the main clock oscillator. the subclock continues to be supplied to keep on-chip peripheral functions operating. if a subclock is not used, ultra low power consumption mode (current that flows through the on-ch ip feedback resistor of the subclock oscillator and leakage current only are flowing) is set. software stop mode setting is pr ohibited if the cpu is oper ating via the subclock. if the stp bit of the psc register is set to 1, the system enters software stop mode. (4) subclock operation in this mode, the cpu clock is set to operate using the subclock and the mck bit of the pcc register is set to 1 to set low power consumption mode in which the entire system operates us ing only the subclock. when halt mode is set, the cpu?s operating clock is stopped so that power c onsumption can be reduced. when idle mode is set, the cpu?s operating clock and so me peripheral functions (dmac and bcu) are stopped, so that power consumption can be r educed even more than in halt mode. 6.4.2 halt mode (1) settings and operating states in this mode, the clock?s oscillator continues to oper ate but the cpu?s operating clock is stopped. a clock continues to be supplied for other on-ch ip peripheral functions to maintain operation of those functions. when halt mode is set while the cpu is idle, it enables the system?s total power c onsumption to be reduced. in halt mode, execution of programs is stopped but the c ontents of all registers and internal ram are retained as they were just before halt mode was set. in addi tion, all on-chip peripheral functions that do not depend on instruction processing by the cpu continue operating. halt mode can be set by executing the halt instruction. it can be set when the cpu is operati ng via either the main clock or subclock. the operating statuses in the halt mode are listed in table 6-1. (2) release of halt mode halt mode can be released by an nmi request, an unma sked maskable interrupt request, or reset input. (a) release by interrupt request halt mode is released regardless of the priority level when an nm i request or an unmasked maskable interrupt request occurs. however, the following occu rs if halt mode was set as part of an interrupt servicing routine. (i) only halt mode is released when an interrupt request t hat has a lower priority level than the interrupt currently being serviced occurs, and the lower-prior ity interrupt request is not acknowledged. the interrupt request itself is retained. (ii) when an interrupt request (including nmi request) that has a higher priority level than the interrupt currently being serviced occurs, halt mode is released and the interrupt request is acknowledged. (b) release by reset pin input this is the same as for normal reset operations.
chapter 6 clock generation function user?s manual u12768ej4v1ud 145 table 6-1. operating statuses in halt mode (1/2) halt mode setting when cpu operates with ma in clock when cpu operates with subclock item when subclock does not exist when subclock exists when main clock?s oscillation continues when main clock?s oscillation is stopped cpu stopped clock generator oscillation for main clock and subclock clock supply to cpu is stopped 16-bit timer (tm0) operating operates when intwti is selected as count clock (f xt is selected for watch timer) 16-bit timer (tm1) operating stopped 8-bit timer (tm2) operating stopped 8-bit timer (tm3) operating stopped 8-bit timer (tm4) operating operates when f xt is selected for count clock 8-bit timer (tm5) operating operates when f xt is selected for count clock watch timer operates when f xx /2 9 is selected for count clock operating operates when f xt is selected for count clock watchdog timer operating (interval timer only) csi0 to csi2 operating operates when an external clock is selected as the serial clock i 2 c note operating stopped serial interface uart0, uart1 operating operates when an external clock is selected as the baud rate clock (transmit only) a/d converter operating stopped dma0 to dma2 operating real-time output operating port function held external bus interface only bus hold function operates nmi operating intp0 to intp3 operating external interrupt request intp4 to intp6 operating stopped note available only in the pd703014ay, 703014by, 703015ay, 703015 by, 703017ay, 70f3015by, and 70f3017ay
chapter 6 clock generation function user?s manual u12768ej4v1ud 146 table 6-1. operating statuses in halt mode (2/2) halt mode setting when cpu operates with ma in clock when cpu operates with subclock item when subclock does not exist when subclock exists when main clock?s oscillation continues when main clock?s oscillation is stopped ad0 to ad15 high impedance note a16 to a21 lben, uben held note (high impedance when hldak = 0) r/w high level output note (high impedance when hldak = 0) dstb, wrl, wrh, rd astb in external expansion mode hldak operating note even when the halt instruction has been executed, the instruction fe tch operation cont inues until the on- chip instruction prefetch queue becomes full. once it is full, operati on stops in the status shown in table 6- 1.
chapter 6 clock generation function user?s manual u12768ej4v1ud 147 6.4.3 idle mode (1) settings and operating states this mode stops the entire system exc ept the watch timer by stopping the on- chip main clock supply while the clock oscillator is still operating. supply to the subclo ck continues. when this mode is released, there is no need for the oscillator to wait for the oscillation stabiliz ation time, so normal operation can be resumed quickly. in idle mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before idle mode was set. in additi on, on-chip peripheral func tions are stopped (except for peripheral functions that are operating with the subclock). exter nal bus hold requests (hldrq) are not acknowledged. when the idle bit of the power save c ontrol register (psc) is set to 1, t he system switches to idle mode. the operating statuses in idle mode are listed in table 6-2. (2) release of idle mode idle mode can be released by a non-maskable interrupt, an unmasked interrupt reques t output from an on-chip peripheral i/o that can be operated, or reset pin input. table 6-2. operating statuses in idle mode (1/2) idle mode settings when subclock exists when subclock does not exist cpu stopped clock generator both main clock and subclock oscillator clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwti is selected as count clock (f xt is selected for watch timer) stopped 16-bit timer (tm1) stopped 8-bit timer (tm2) stopped 8-bit timer (tm3) stopped 8-bit timer (tm4) operates when f xt is selected for count clock stopped 8-bit timer (tm5) operates when f xt is selected for count clock stopped watch timer operates when f xt is selected for count clock stopped watchdog timer stopped csi0 to csi2 operates when an external clock is selected as the serial clock i 2 c note stopped serial interface uart0, uart1 operates when an external clock is select ed as the baud rate clock (transmit only) a/d converter stopped dma0 to dma2 stopped real-time output operates when inttm4 or inttm5 is selected (when tm4 or tm5 is operating) stopped note available only in the pd703014ay, 703014by, 703015ay, 703015 by, 703017ay, 70f3015by, and 70f3017ay item
chapter 6 clock generation function user?s manual u12768ej4v1ud 148 table 6-2. operating statuses in idle mode (2/2) idle mode settings when subclock exists when subclock does not exist port function held external bus interface stopped nmi operating intp0 to intp3 operating external interrupt request intp4 to intp6 stopped ad0 to ad15 a16 to a21 lben, uben r/w dstb, wrl, wrh, rd astb in external expansion mode hldak high impedance 6.4.4 software stop mode (1) settings and operating states this mode stops the entire system by st opping the main clock oscillator to stop supplying the internal main clock. the subclock oscillator continues operating and the on-chip subclock supply is continued. when the subclock is not used, low pow er consumption of only the current flowing thr ough the on-chip feed-back resistor and leakage current is realized. in this mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before software stop mode was set. on-c hip peripheral functions also stop operation (peripheral functions operating on the subclo ck are not stopped). external bus hold requests (hldrq) are not acknowledged. this mode can be set only when the main clock is being us ed as the cpu clock. this mode is set when the stp bit in the power save control register (psc) has been set to 1. do not set this mode when the subclo ck has been selected as the cpu clock. the operating statuses in software st op mode are listed in table 6-3. (2) release of software stop mode software stop mode can be released by a non-maskable interrupt, an unmasked interrupt request output from an on-chip peripheral i/o that c an be operated, or reset input. when the software stop mode is released, the oscillation stabilization time is secured. item
chapter 6 clock generation function user?s manual u12768ej4v1ud 149 table 6-3. operating statuses in software stop mode software stop mode settings item when subclock exists when subclock does not exist cpu stopped clock generator oscillation for main clock is stopped and oscillation for subclock continues clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwti is selected for count clock (f xt is selected as count clock for watch timer) stopped 16-bit timer (tm1) stopped 8-bit timer (tm2) stopped 8-bit timer (tm3) stopped 8-bit timer (tm4) operates when f xt is selected for count clock stopped 8-bit timer (tm5) operates when f xt is selected for count clock stopped watch timer operates when f xt is selected for count clock stopped watchdog timer stopped csi0 to csi2 operates when an external clock is selected as the serial clock i 2 c note stopped serial interface uart0, uart1 operates when an external clock is select ed as the baud rate clock (transmit only) a/d converter stopped dma0 to dma2 stopped real-time output operates when inttm4 or inttm5 has been selected (when tm4 or tm5 is operating) stopped port function held external bus interface stopped nmi operating intp0 to intp3 operating external interrupt request intp4 to intp6 stopped ad0 to ad15 a16 to a21 lben, uben r/w dstb, wrl, wrh, rd astb in external expansion mode hldak high impedance note available only in the pd703014ay, 703014by, 703015ay, 703015 by, 703017ay, 70f3015by, and 70f3017ay
chapter 6 clock generation function user?s manual u12768ej4v1ud 150 6.5 oscillation stabilization time the following shows the methods for spec ifying the length of the oscillation st abilization time required to stabilize the oscillator following release of software stop mode. (1) release non-maskable interrupt or by unmasked interrupt request software stop mode is released by a non-maskable in terrupt or an unmasked interrupt request. when an interrupt is input to this pin, the counter (watchdog timer) starts counting and the count time is the length of time that must elapse for stabilization of the oscillator?s clock output. the oscillation stabilization time is set by the osc illation stabilization time se lect register (osts). oscillation stabilization time = wdt count time after the specified amount of time has elapsed, system clock output st arts and processing branches to the interrupt handler address. figure 6-2. oscillation stabilization time software stop mode is set oscillator is stopped oscillation stabilization time count oscillation wave main clock stop status interrupt input (2) use of reset pin to secure time (reset pin input) for securing time with the reset pin, refer to chapter 15 reset function . the oscillation stabilization time is 2 19 /fxx according to the value of the osts register after reset.
chapter 6 clock generation function user?s manual u12768ej4v1ud 151 6.6 cautions on power save function (1) while an instruction is being executed on internal rom to set the power save mode (idle mode or software st op mode) while an instruct ion is being executed on the internal rom, insert a nop instructi on as a dummy instruction to correctly execute the routine after releasing the power save mode. the following shows the sequence of setting the power save mode. <1> disable dma operation. <2> disable interrupts (set np bit of psw to 1). <3> write 8-bit data to the command register (prcmd). <4> write setting data to the power save control r egister (psc) (using the following instructions). ? store instruction (s t/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> clear the interrupt disabled state (re -set the np bit of the psw to 0). <6> insert nop instructions (2 or 5 instructions). <7> if dma operation is necessary, enable dma operation. cautions 1. insert two nop instructions if the id bi t value of the psw is not changed by the execution of the instruction that clear s the np bit to 0 (<5>), and insert five nop instructions if changed. the following shows a description example. [description example] : when using psc register ldsr rx.5 ; np bit = 1 st.b r0, prcmd[r0] ; write to prcmd st.b rd, rsc[r0] ; psc register setting ldsr ry, 5 ; np bit = 0 nop ; dummy instructions (2 or 5 instructions) : nop (next instruction) ; execution routine after releasing idle/software stop mode : rx: value to be written to psw ry: value to be rewritten to psw rd: value to be set to psc when saving the psw value, transfer the psw value before setting the np bit to the ry register. 2. the instructions (<5> interrupt disable clear, <6> nop instruction) following the store instruction to the psc register for setting the idle mode and software stop mode are executed before entering the power save mode.
chapter 6 clock generation function user?s manual u12768ej4v1ud 152 (2) while an instruction is being executed on external rom (i) do not set the power save mode (idle or softwar e stop mode) while an inst ruction is being executed on the external rom. (ii) to set the power save mode (idle or software st op mode) while an instruct ion is being executed on the external rom, handle as follows. <1> insert six nop instructions 4 bytes after the instruction that writes to the psc register. <2> insert the br $+2 instruction following the nop in struction to eliminate t he discrepancy of the program counter (pc). [processing program example] ldsr rx.5 ; np bit = 1 st.b r0, prcmd[r0] ; write to prcmd st.b rd, rsc[r0] ; psc register setting ldsr ry, 5 ; np bit = 0 nop ; nop instruction (6 instructions) nop nop nop nop nop br $+2 ; eliminate discrepancy of pc rx: value to be written to psw ry: value to be rewritten to psw rd: value to be set to psc
user?s manual u12768ej4v1ud 153 chapter 7 timer/counter function 7.1 16-bit timers (tm0, tm1) 7.1.1 outline 16-bit capture/compare regi sters: 2 (crn0, crn1) independent capture/trigger i nputs: 2 (tin0, tin1) support of output of capt ure/match interrupt request signals (inttmn0, inttmn1) event input (shared with tin0) via digital noi se eliminator and suppor t of edge specification timer output operated by matc h detection: 1 each (ton) when using the p34/to0 and p 35/to1 pins as the to0 and to 1 pins (timer output), set the value of port 3 (p3) to 0 (low-level output) and the port 3 mode register (pm3) to 0 (port output mode). the logical sum (ored) value of the output of the port and the timer is output. remark n = 0, 1 7.1.2 functions tm0 and tm1 have the following functions. interval timer ppg output pulse width measurement external event counter square wave output one-shot pulse output the block diagram is shown below.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 154 figure 7-1. block diagram of tm0 and tm1 note the count clock is set by the prmn and prmn1 registers. remark n = 0, 1 (1) interval timer generates an interrupt at pr edetermined time intervals. (2) ppg output can output a square wave whose frequency and out put pulse width can be changed arbitrarily. (3) pulse width measurement can measure the pulse width of a si gnal input from an external source. (4) external event counter can measure the number of pulses of a signal input from an external source. (5) square wave output can output a square wave of any frequency. match clear noise eliminator noise eliminator noise eliminator selector selector selector selector 16-bit capture/compare register n0 (crn0) 16-bit capture/compare register n1 (crn1) 16-bit timer register (tmn) match inttmn0 ton inttmn1 internal bus capture/compare control register n (crcn) prescaler mode register n1 (prmn1) prescaler mode register n (prmn) 16-bit timer mode control register n (tmcn) timer output control register n (tocn) tln1 f xx /2 tln0 3 crcn2 prmn2 prmn1 crcn2 crcn1 crcn0 prmn0 tmcn3 tmcn2 tmcn1 ovfn osptn ospen tocn4 lvsn lvrn tocn1 toen count clock note internal bus output controller
chapter 7 timer/counter function user?s manual u12768ej4v1ud 155 (6) one-shot pulse output can output a one-shot pulse with any output pulse width. 7.1.3 configuration timers 0 and 1 consist of the following hardware. table 7-1. configuration of timers 0 and 1 item configuration timer registers 16 bits 2 (tm0, tm1) registers capture/compare registers: 16 bits 2 (crn0, crn1) timer outputs 2 (to0, to1) control registers 16-bit timer mode cont rol registers 0, 1 (tmc0, tmc1) capture/compare control registers 0, 1 (crc0, crc1) 16-bit timer output control registers 0, 1 (toc0, toc1) prescaler mode register n, n1 (prmn, prmn1) remark n = 0, 1 (1) 16-bit timer registers 0, 1 (tm0, tm1) tmn is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the i nput clock. if the count value is read during operation, input of the count clock is temporar ily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmcn3 and tmcn2 are cleared <3> if the valid edge of tin0 is input in the mode in which the timer is created and started on inputting the valid edge of tin0 <4> if tmn and crn0 match in the clear and st art mode entered on a match between tmn and crn0 <5> if osptn is set or if the valid edge of ti n0 is input in the one- shot pulse output mode
chapter 7 timer/counter function user?s manual u12768ej4v1ud 156 (2) capture/compare regist ers 00, 10 (cr00, cr10) crn0 is a 16-bit register that functions as a capture register and as a compare register. whether this register functions as a capture or compare register is specified by using bi t 0 (crcn0) of the crcn register. (a) when using crn0 as compare register the value set to crn0 is always com pared with the count value of the tmn register. when the values of the two match, an interrupt request (in ttmn0) is generated. when tmn is us ed as an interval timer, crn0 can also be used as a register that holds the interval time. (b) when using crn0 as capture register the valid edge of the tin0 or tin1 pin can be selected as a capture trigger. the valid edge of tin0 or tin1 is set by using the prmn register. when the valid edge of the tin0 pin is spec ified as the capture trigger, refer to table 7-2 . when the valid edge of the tin1 pin is specified as the capture trigger, refer to table 7-3 . table 7-2. valid edge of tin0 pin and capture trigger of crn0 esn01 esn00 valid edge of tin0 pin crn0 capture trigger 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation remark n = 0, 1 table 7-3. valid edge of tin1 pin and capture trigger of crn0 esn11 esn10 valid edge of tin1 pin crn0 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0, 1 crn0 is set by using a 16-bit memory manipulation instruction. these registers can be read/writt en when used as compare register s and can only be read when used as capture registers. reset input sets this register to 0000h. caution in a mode in which the timer is clear ed and started on a match between tmn and crn0, set the crn0 register to othe r than 0000h. in the free-running mode or the tin0 valid edge clear mode, however, an in terrupt request (inttmn0) is generated after an overflow (ffffh) when crn0 is set to 0000h.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 157 (3) capture/compare regist ers 01, 11 (cr01, cr11) this is a 16-bit register that can be used as a capture register and a compare register. whether it is used as a capture register or compare r egister is specified by bit 2 (crcn2) of the crcn register. (a) when using crn1 as compare register the value set to crn1 is always com pared with the count value of tmn. when the val ues of the two match, an interrupt request (inttmn1) is generated. (b) when using crn1 as capture register the valid edge of the tin0 pin can be se lected as a capture trigger. the valid edge of tin0 is specified by using the prmn register. table 7-4. valid edge of tin0 pin and capture trigger of crn1 esn01 esn00 valid edge of tin0 pin crn1 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0, 1 crn1 is set by using a 16-bit memory manipulation inst ruction. these registers can be read/written when used as compare registers and can only be r ead when used as capt ure registers. the value of this register is set to 0000h after the reset signal is input. caution in a mode in which the timer is clear ed and started on a match between tmn and crn0, set the crn1 register to othe r than 0000h. in the free-running mode or the tin0 valid edge clear mode, however, an in terrupt request (inttmn1) is generated after an overflow (ffffh) when crn1 is set to 0000h.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 158 7.1.4 timer 0, 1 control registers the following four types of regi sters control timers 0 and 1. 16-bit timer mode control register n (tmcn) capture/compare contro l register n (crcn) 16-bit timer output control register n (tocn) prescaler mode register n, n1 (prmn, prmn1) remark n = 0, 1 (1) 16-bit timer mode control re gisters 0, 1 (tmc0, tmc1) tmcn specifies the operation mode of the 16-bit timer, and the clear m ode, output timing, and overflow detection of 16-bit timer register n. tmcn is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc0 and tmc1 to 00h. caution 16-bit timer register n starts operating wh en tmcn2 and tmcn3 are set to values other than 0, 0 (operation stop mode). to stop the ope ration, set tmcn2 and tmcn3 to 0, 0.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 159 after reset: 00h r/w address: fffff208h, fffff218h 7 6 5 4 3 2 1 0 tmcn 0 0 0 0 tmcn3 tmcn2 tmcn1 ovfn (n = 0, 1) tmcn3 tmcn2 tmcn1 operation mode and clear mode selection ton output timing selection generation of interrupt 0 0 0 operation stops (tmn is cleared to 0) not affected not generated 0 0 1 0 1 0 free-running mode match between tmn and crn0 or match between tmn and crn1 0 1 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 generated on match between tmn and crn0 and match between tmn and crn1 1 0 0 clears and starts at valid edge of tin0 match between tmn and crn0 or match between tmn and crn1 1 0 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 1 1 0 clears and starts on match between tmn and crn0 match between tmn and crn0 or match between tmn and crn1 1 1 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 ovfn detection of overflow of 16-bit timer register n 0 did not overflow 1 overflowed cautions 1. when a bit other than the ovfn flag is written, be sure to stop the timer operation. 2. the valid edge of the tin0 pin is set by using prescaler mode register n (prmn). 3. when a mode in which the timer is cleared and started on a match between tmn and crn0 is selected, the ovfn flag is set to 1 when the count value of tmn changes from ffffh to 0000h with crn0 set to ffffh. 4. be sure to set bits 4 to 7 to 0. remark ton: output pin of timer n tin0: input pin of timer n tmn: 16-bit timer register n crn0: compare register n0 crn1: compare register n1
chapter 7 timer/counter function user?s manual u12768ej4v1ud 160 (2) capture/compare control registers 0, 1 (crc0, crc1) crcn controls the operation of capture/compare regi ster n (crn0 and crn1). crcn is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc0 and crc1 to 00h. after reset: 00h r/w address: fffff20ah, fffff21ah 7 6 5 4 3 2 1 0 crcn 0 0 0 0 0 crcn2 crcn1 crcn0 (n = 0, 1) crcn2 selection of operation mode of crn1 0 operates as compare register 1 operates as capture register crcn1 selection of capture trigger of crn0 0 captured at valid edge of tin1 1 captured in reverse phase of valid edge of tin0 crcn0 selection of operation mode of crn0 0 operates as compare register 1 operates as capture register cautions 1. before setting crcn, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started on a match between tmn and crn0 is selected by 16-bit timer mode contro l register n (tmcn), do not specify crn0 as a capture register. 3. when both the rising edge and falling edge are specified fo r the tin0 valid edge, the capture operation does not work. 4. to ensure that the capture tr igger captures the signals from tin0 and tin1 correctly, a pulse longer than two of the c ount clocks selected by prescaler mode registers n and n1 (prmn, prmn1) is required. 5. be sure to set bits 3 to 7 to 0.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 161 (3) 16-bit timer output control registers 0, 1 (toc0, toc1) tocn controls the operation of the timer n output controller by setting or resetting the r-s flip-flop (lv0), enabling or disabling reverse output, enabling or disabling output of timer n, enabli ng or disabling one-shot pulse output operation, and selecting the output trigger for the one-shot pulse by software. tocn is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc0 and toc1 to 00h. after reset: 00h r/w address: fffff20ch, fffff21ch 7 6 5 4 3 2 1 0 tocn 0 osptn ospen tocn4 lvsn lvrn tocn1 toen (n = 0, 1) osptn control of output trigger of one-shot pulse by software 0 no one-shot pulse trigger 1 one-shot pulse trigger used ospen control of one-shot pulse output operation 0 successive pulse output 1 one-shot pulse output note tocn4 control of timer output f/f on match between crn1 and tmn 0 reverse timer output f/f disabled 1 reverse timer output f/f enabled lvsn lvrn setting of status of timer output f/f of timer n 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited tocn1 control of timer output f/f on match between crn0 and tmn 0 reverse timer output f/f disabled 1 reverse timer output f/f enabled toen control of output of timer n 0 output disabled (output is fixed to 0 level) 1 output enabled note the one-shot pulse out put operates normally in the free-r unning mode and clear and start mode set by the valid edge of tin0. cautions 1. before setting tocn, be sure to stop the timer operation. 2. lvsn and lvrn are 0 when read after data has been set to them. 3. osptn is 0 when read because it is au tomatically cleared afte r data has been set. 4. do not set osptn other than for one-shot pulse output.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 162 (4) prescaler mode registers 0, 01 (prm0, prm01) prm0 and prm01 select the count cl ock of the 16-bit timer (tm0) and t he valid edge of ti0n input. prm0 and prm01 are set by an 8-bit memo ry manipulation instruction. reset input clears prm0 and prm01 to 00h. remark n = 0, 1 after reset: 00h r/w address: fffff20eh 7 6 5 4 3 2 1 0 prm01 0 0 0 0 0 0 0 prm02 after reset: 00h r/w address: fffff206h 7 6 5 4 3 2 1 0 prm0 es011 es010 es001 es000 0 0 prm01 prm00 es011 es010 selection of valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es001 es000 selection of valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f xx prm02 prm01 prm00 count clock 20 mhz 17 mhz 10 mhz 2 mhz 0 0 0 f xx /2 100 ns 118 ns 200 ns 1 s 0 0 1 f xx /16 800 ns 941 ns 1.6 s 8 s 0 1 0 intwti ? ? ? ? 0 1 1 ti00 valid edge note ? ? ? ? 1 0 0 f xx /4 200 ns 235 ns 400 ns 2 s 1 0 1 f xx /64 3.2 s 3.8 s 6.4 s 32 s 1 1 0 f xx /256 12.8 s 15.1 s 25.6 s 128 s 1 1 1 setting prohibited ? ? ? ? note the external clock requires a pulse longer than two internal clocks (f xx /2).
chapter 7 timer/counter function user?s manual u12768ej4v1ud 163 cautions 1. when selecting the valid edge of ti00 as the count clock, do not specify the valid edge of ti00 to clear and start the ti mer and as a capture trigger. 2. before setting data to th e prm0 and prm01 registers, always stop the timer operation. 3. if the 16-bit timer (tm0) operation is enable d by specifying the rising edge or both edges as the valid edge of the ti0n pin while the ti0n pin is high level immediately after system reset, the rising edge is detected imme diately after the rising edge or both edges is specified. be careful when pulling up the ti0n pin. how ever, the rising edge is not detected when operation is enabled after it has been stopped.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 164 (5) prescaler mode registers 1, 11 (prm1, prm11) prm1 and prm11 select the count cl ock of the 16-bit timer (tm1) and t he valid edge of ti1n input. prm1 and prm11 are set by an 8-bit memo ry manipulation instruction. reset input clears prm1 and prm11 to 00h. remark n = 0, 1 after reset: 00h r/w address: fffff21eh 7 6 5 4 3 2 1 0 prm11 0 0 0 0 0 0 0 prm12 note after reset: 00h r/w address: fffff216h 7 6 5 4 3 2 1 0 prm1 es111 es110 es101 es100 0 0 prm11 prm10 es111 es110 selection of valid edge of ti11 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es101 es100 selection of valid edge of ti10 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f xx prm12 prm01 prm00 count clock 20 mhz 17 mhz 10 mhz 2 mhz 0 0 0 f xx /2 100 ns 118 ns 200 ns 1 s 0 0 1 f xx /4 200 ns 235 ns 400 ns 2 s 0 1 0 f xx /16 800 ns 941 ns 1.6 s 8 s 0 1 1 ti10 valid edge note ? ? ? ? 1 0 0 f xx /32 1.6 s 1.9 s 3.2 s 16 s 1 0 1 f xx /128 6.4 s 7.5 s 12.8 s 64 s 1 1 0 f xx /256 12.8 s 15.1 s 25.6 s 128 s 1 1 1 setting prohibited ? ? ? ? note the external clock requires a pulse longer than two internal clocks (f xx /2).
chapter 7 timer/counter function user?s manual u12768ej4v1ud 165 cautions 1. when selecting the valid edge of ti10 as the count clock, do not specify the valid edge of ti10 to clear and start the ti mer and as a capture trigger. 2. before setting data to th e prm1 and prm11 registers, always stop the timer operation. 3. if the 16-bit timer (tm1) operation is enable d by specifying the rising edge or both edges for the valid edge of the ti1n pin while the ti1n pin is high level immediately after system reset, the rising edge is detected imme diately after the rising edge or both edges is specified. be careful when pulling up ti1n pin. however, the ri sing edge is not detect ed when operation is enabled after it has been stopped.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 166 7.2 16-bit timer operation 7.2.1 operation as inter val timer (16 bits) tmn operates as an interval timer when 16-bit timer mode control register n (tmcn) and capture/compare control register n (crcn) are set as shown in figure 7-2. in this case, tmn repeatedly generates an in terrupt at the time interval specif ied by the count value set in advance to 16-bit capture/compare register n0 (crn0). when the count value of tmn matches the set value of crn0, the value of tmn is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttmn0) is generated. the count clock of the 16-bit timer/ev ent counter can be selected by bits 0 and 1 (prmn0 and prmn1) of prescaler mode register n (prmn) and by bit 0 (prmn2) of prescaler mode register n1 (prmn1). remark n = 0, 1 figure 7-2. control register settings when tmn operates as interval timer (a) 16-bit timer mode control re gisters 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 1 1 0/1 0 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 used as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used al ong with the interval timer function. for details, refer to 7.1.4 (1) 16-bit timer mode contro l registers 0, 1 (tmc0, tmc1) and 7.1.4 (2) capture/compare cont rol registers 0, 1 (crc0, crc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 167 figure 7-3. configuration of interval timer note the count clock is set by the prmn and prmn1 registers. remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. n = 0, 1 figure 7-4. timing of interval timer operation t interval time interval time interval time 0000h n 0001h 0001h 0000h nn n n n n 0001h 0000h count start clear interrupt acknowledgement count clock tmn count value crn0 ton inttmn0 interrupt acknowledgement clear remarks 1. interval time = (n + 1) t: n = 0001h to ffffh 2. n = 0,1 16-bit capture/compare register n0 (crn0) 16-bit timer register n (tmn) selector ovfn inttmn0 count clock note tin0 clear circuit noise eliminator fxx/2
chapter 7 timer/counter function user?s manual u12768ej4v1ud 168 7.2.2 ppg output operation tmn can be used for ppg (programmable pulse generator) output by setting 16- bit timer mode control register n (tmcn) and capture/compare c ontrol register n (crcn) as shown in figure 7-5. the ppg output function outputs a square wave from the ton pin at the cycle specified by the count value set in advance to 16-bit capture/compare regist er n0 (crn0) and the pulse width specif ied by the count value set in advance to 16-bit capture/compare register n1 (crn1). remark n = 0, 1 figure 7-5. control register se ttings in ppg output operation (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 1 1 0 0 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0 crn0 used as compare register crn1 used as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn 0 0 0 1 0/1 0/1 1 1 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. reverses output on match between tmn and crn1. disables one-shot pulse output. cautions 1. make sure that crn0 a nd crn1 are set to 0000h < crn1 < crn0 ffffh. 2. ppg output set the pulse cycl e to (crn0 set value + 1). the duty factor is (crn1 set value + 1)/(crn0 set value + 1). : don?t care
chapter 7 timer/counter function user?s manual u12768ej4v1ud 169 7.2.3 pulse width measurement 16-bit timer register n (tmn) can be used to measure t he pulse widths of the signal s input to the tin0 and tin1 pins. measurement can be carried out with tmn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the tin0 pin. (1) pulse width measurement with free runni ng counter and one capture register if the edge specified by prescaler mode r egister n (prmn) is input to the tin0 pin when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 7-6 ), the value of tmn is loaded to 16-bit capture/compare register n1 (cr n1), and an external interrupt request signal (inttmn1) is set. the edge is specified by using bits 6 and 7 (esn10 and esn11) of prescaler m ode register n (prmn). the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected by sampling at the count clock cycle selected by pr escaler mode register n, n1 (prmn, prmn1), and a capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. remark n = 0, 1 figure 7-6. control register setti ngs for pulse width measurement with free-running counter a nd one capture register (a) 16-bit timer mode control re gisters 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 0 1 0/1 0 free-running mode (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 0/1 0 crn0 used as compare register crn1 used as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) and 7.1.4 (2) capture/compare c ontrol registers 0, 1 (crc0, crc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 170 figure 7-7. configuration for pulse wi dth measurement with free-running counter 16-bit timer register n (tmn) 16-bit capture/compare register n1 (crn1) selector ovfn inttmn1 internal bus tin0 count clock note note the count clock is set by the prmn and prmn1 registers. remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. n = 0, 1 figure 7-8. timing of pulse width m easurement with free-running counter and one capture register (wit h both edges specified) remark n = 0, 1 t 0000h 0000h ffffh 0001h d0 d0 + 1 d1 d0 d1 d2 d3 d2 d3 d1 + 1 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t count clock tmn count value tin0 pin input value loaded to crn1 inttmn1 ovfn
chapter 7 timer/counter function user?s manual u12768ej4v1ud 171 (2) measurement of two pulse widths with free running counter the pulse widths of the two signals respectively input to the tin0 and tin1 pins can be measured when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 7-9 ). when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode regi ster n (prmn) is input to the tin0 pin, the value of tmn is loaded to 16-bit capture/compare register n1 (crn1) and an external interrupt request signal (inttmn1) is set. when the edge specified by bits 6 and 7 ( esn10 and esn11) in prmn is input to the tin1 pin, the value of tmn is loaded to 16-bit capture/compare regist er n0 (crn0), and an external interrupt request signal (inttmn0) is set. the edges of the tin0 and ti n1 pins are specified by bits 4 and 5 (esn00 and esn01) and bits 6 and 7 (esn10 and esn11) of prmn0, respectively. the rising, fa lling, or both rising and falli ng edges can be specified. the valid edge is detected by sampling at the count clock cycle selected by pr escaler mode register n, n1 (prmn, prmn1), and a capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. remark n = 0, 1 figure 7-9. control register settings for measure ment of two pulse widths with free-running counter (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 0 1 0/1 0 free-running mode (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 0 1 crn0 used as capture register captures valid edge of tin1 pin to crn0. crn1 used as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) and 7.1.4 (2) capture/compare c ontrol registers 0, 1 (crc0, crc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 172 capture operation (free running mode) the following figure illustrates the operation of the capture register when the capture trigger is input. figure 7-10. crn1 capture operat ion with rising edge specified remark n = 0, 1 figure 7-11. timing of pulse width measurement wit h free-running counter (with both edges specified) remark n = 0, 1 n ? 3n ? 2n ? 1 n n + 1 n count clock tmn crn1 inttmn1 tin0 rising edge detection t 0000h 0001h ffffh 0000h d0 d0 + 1 d1 d0 d1 d1 d2 + 1 d2 d1 + 1 d2 d3 d2 + 1 d2 + 2 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t count clock tmn count value tin0 pin input tin1 pin input value loaded to crn1 value loaded to crn0 inttmn1 inttmn0 ovfn
chapter 7 timer/counter function user?s manual u12768ej4v1ud 173 (3) pulse width measurement with free r unning counter and two capture registers when 16-bit timer register n (tmn) is used as a free running counter (refer to figure 7-19 ), the pulse width of the signal input to the tin0 pin can be measured. when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode regi ster n (prmn) is input to the tin0 pin, the value of tmn is loaded to 16-bit capture/compare register n1 (crn1), and an external interrupt request signal (inttmn1) is set. the value of tmn is also loaded to 16-bit capture/compare register n0 (crn0) when an edge reverse to the one that triggers capturing to crn1 is input. the edge of the tin0 pin is s pecified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n (prmn). the rising or falling edge can be eliminated. the valid edge of tin0 is detec ted by sampling at the count clock cycle se lected by prescaler mode register n, n1 (prmn, prmn1), and the capt ure operation is not perform ed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform its capture operation. remark n = 0, 1 figure 7-12. control register setti ngs for pulse width measurement with free-running counter a nd two capture registers (a) 16-bit timer mode control re gisters 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 0 1 0/1 0 free-running mode (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 1 1 crn0 used as capture register captures to crn0 at edge reverse to valid edge of tin0 pin. crn1 used as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) and 7.1.4 (2) capture/compare c ontrol registers 0, 1 (crc0, crc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 174 figure 7-13. timing of pulse width m easurement with free-running counter and two capture registers (with rising edge specified) remark n = 0, 1 (4) pulse width measurement by restarting when the valid edge of the tin0 pin is detected, the pulse width of the signal input to the tin0 pin can be measured by clearing 16-bit timer register n (tmn) onc e and then resuming counting after loading the count value of tmn to 16-bit capture/com pare register n1 (crn1) (see figure 7-13 ). the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode r egister n (prmn). the rising or falling edge can be specified. the valid edge is detected by sampling at the count clock cycle selected by pr escaler mode register n, n1 (prmn, prmn1) and the capture operati on is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform its capture operation. remark n = 0, 1 t 0000h 0001h ffffh 0000h d0 d0 d1 d3 d2 d0 + 1 d1 d1 + 1 d2 d3 d2 + 1 count clock tmn count value tin0 pin input value loaded to crn1 value loaded to crn0 inttmn1 ovfn (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t
chapter 7 timer/counter function user?s manual u12768ej4v1ud 175 figure 7-14. control register settings fo r pulse width measurement by restarting (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 1 0 0/1 0 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 1 1 crn0 used as capture register captures to crn0 at edge reverse to valid edge of tin0. crn1 used as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) and 7.1.4 (2) capture/compare c ontrol registers 0, 1 (crc0, crc1) . figure 7-15. timing of pulse width measurement by restarting (with rising edge specified) remark n = 0, 1 t (d1 + 1) t (d2 + 1) t d0 d0 d2 d1 d1 d2 0001h 0000h 0001h 0000h 0001h 0000h count clock tmn count value tin0 pin input inttmn1 value loaded to crn1 value loaded to crn0
chapter 7 timer/counter function user?s manual u12768ej4v1ud 176 7.2.4 operation as external event counter tmn can be used as an external event c ounter that counts t he number of clock pulses input to the tin0 pin from an external source by using 16-bit timer register n (tmn). each time the valid edge specified by prescaler mode register n (prmn) has been input, tmn is incremented. when the count value of tmn matches t he value of 16-bit capture/ compare register n0 (crn0), tmn is cleared to 0, and an interrupt request signal (inttmn0) is generated. the edge is specified by bits 4 and 5 ( esn00 and esn01) of prescaler mode regist er n (prmn). the rising, falling, or both the rising and falli ng edges can be specified. the valid edge is detected by samp ling at a count clock cycle of f xx /2, and a capture operation is not performed until the valid level is detected two times. therefore, noise with a s hort pulse width can be eliminated. remark n = 0, 1 figure 7-16. control register settings in external event counter mode (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 1 1 0/1 0 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 used as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the external event counter function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) and 7.1.4 (2) capture/compare cont rol registers 0, 1 (crc0, crc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 177 figure 7-17. configuration of external event counter note the count clock is set by the prmn and prmn1 registers. remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. n = 0, 1 figure 7-18. timing of external event count er operation (with rising edge specified) 0000h 0001h 0002h 0003h 0000h 0001h 0002h 0003h 0004h 0005h n ? 1n n tin0 pin input tmn count value crn0 inttmn0 caution read tmn when reading the c ount value of the external event counter. remark n = 0, 1 16-bit capture/compare register n0 (crn0) 16-bit timer/counter n (tmn) 16-bit capture/compare register n1 (crn1) selector ovfn inttmn0 count clock note fxx/2 valid edge of tin0 internal bus noise eliminator match clear
chapter 7 timer/counter function user?s manual u12768ej4v1ud 178 7.2.5 operation to output square wave tmn can be used to output a square wave with any frequency at the interval s pecified by the count value set in advance to 16-bit capture/co mpare register n0 (crn0). by setting bits 0 (toen) and 1 (tocn1) of 16-bit timer output c ontrol register n (tocn) to 1, the output st atus of the ton pin is reversed at the interval specif ied by the count value set in advance to crn1. in this way, a square wave of any frequency can be output. remark n = 0, 1 figure 7-19. control register setti ngs in square wave output mode (a) 16-bit timer mode control re gisters 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 1 1 0 0 clears and starts on match between tmn and crn0. (b) capture/compare contro l registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 1 crn0 used as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn 0 0 0 0 0/1 0/1 1 1 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. does not reverse output on match between tmn and crn1. disables one-shot pulse output. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the square wave output function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1), 7.1.4 (2) capture/comp are control registers 0, 1 (crc0, crc1) , and 7.1.4 (3) 16-bit timer output control registers 0, 1 (toc0, toc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 179 figure 7-20. timing of square wave output operation 0000h 0001h 0002h 0000h 0001h 0002h n ? 1n n 0000h n ? 1n count clock tmn count value crn0 inttmn0 ton pin output remark n = 0, 1 7.2.6 operation to output one-shot pulse tmn can output a one-shot pulse in synch ronization with a software trigger and an external trigger (tin0 pin input). (1) one-shot pulse output with software trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control regi ster n (crcn), and 16-bit timer output contro l register n (tocn) as shown in figure 7-21, and by setting bit 6 (osptn) of tocn by software. by setting osptn to 1, the 16-bit ti mer/event counter is cl eared and started, and its out put is asserted at the count value (n) set in advance to 16-bi t capture/compare register n1 (crn1). after that, the output is deasserted at the count value (m) set in advance to 16-bit capture/compar e register n0 (crn0) note . even after the one-shot pulse has been out put, tmn continues its operation. to stop tmn, tmcn must be reset to 00h. note this is an example when n < m. when n > m, output of crn0 is assert ed and output of crn1 is deasserted. cautions 1. do not set osptn to 1 while the one-shot pulse is being output . to output the one-shot pulse again, wait until the current one-shot pulse output is complete. 2. during a one-shot pulse output operation star ted by a software trigger, the tin0 pin cannot be used as a general-purpose port. remark n = 0, 1
chapter 7 timer/counter function user?s manual u12768ej4v1ud 180 figure 7-21. control register settings for one-shot pulse output with software trigger (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 0 1 0 0 free-running mode (b) capture/compare contro l registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0/1 0 crn0 used as compare register crn1 used as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn 0 0 1 1 0/1 0/1 1 1 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. reverses output on match between tmn and crn1. sets one-shot pulse output mode. set to 1 for output. caution do not set the crn0 and crn1 registers to 0000h. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the one- shot pulse output function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1), 7.1.4 (2) capture/compare c ontrol registers 0, 1 (crc0, crc1) , and 7.1.4 (3) 16-bit timer output contro l registers 0, 1 (toc0, toc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 181 figure 7-22. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h 0000h 0001h 0000h count clock tmn count value crn1 set value crn0 set value osptn inttmn1 inttmn0 ton pin output set 0ch to tmcn (tmn count starts) caution 16-bit timer register n starts operati ng as soon as tmcn2 and tmcn3 have been set to values other than 0, 0 (operation stop mode). remark n = 0, 1 n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control regi ster n (crcn), and 16-bit timer output contro l register n (tocn) as shown in figure 7-23, and by using the valid edge of t he tin0 pin as an external trigger. the valid edge of the tin0 pin is s pecified by bits 4 and 5 (esn00 and es n01) of prescaler mode register n (prmn). the rising, falling, or both t he rising and falling edges can be specified. when the valid edge of the tin0 pin is detected, the 16-bit timer/event c ounter is cleared and started, and the output is asserted at the count val ue (n) set in advance to 16-bit captur e/compare register n1 (crn1). after that, the output is deasserted at the count value (m) set in advance to 16-bit capture/compare register n0 (crn0) note . note this is an example when n < m. when n > m, output of crn0 is asse rted and output of crn1 is deasserted. caution even if the external tri gger is generated again while th e one-shot pulse is output, it is ignored. remark n = 0, 1
chapter 7 timer/counter function user?s manual u12768ej4v1ud 182 figure 7-23. control register settings for on e-shot pulse output with external trigger (a) 16-bit timer mode control re gisters 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn 0 0 0 0 1 0 0 0 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0/1 0 crn0 used as compare register crn1 used as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn 0 0 1 1 0/1 0/1 1 1 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. reverses output on match between tmn and crn1. sets one-shot pulse output mode. caution do not set the crn0 and crn1 registers to 0000h. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the one-shot pulse output function. for details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1), 7.1.4 (2) capture/comp are control registers 0, 1 (crc0, crc1) , and 7.1.4 (3) 16-bit timer output control registers 0, 1 (toc0, toc1) .
chapter 7 timer/counter function user?s manual u12768ej4v1ud 183 figure 7-24. timing of one-shot pulse output operati on with external trigger (with rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2m ? 1 0001h 0000h count clock tmn count value crn1 set value crn0 set value tin0 pin input inttmn1 inttmn0 ton pin output set 08h to tmcn (tmn count starts) caution 16-bit timer register n starts operati ng as soon as tmcn2 and tmcn3 have been set to values other than 0, 0 (operation stop mode). remark n = 0, 1 n < m
chapter 7 timer/counter function user?s manual u12768ej4v1ud 184 7.2.7 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 16-bit timer register n (tmn) is st arted asynchronously to the count pulse. figure 7-25. start timing of 16-bit timer register n 0000h timer starts 0001h 0002h 0003h 0004h count pulse tmn count value remark n = 0, 1 (2) setting 16-bit capture/compare regi ster (in mode in which clear & start occurs on match between tmn and crn0) set 16-bit capture/compare register s n0 and n1 (crn0, crn1) to a value other than 0000h. when using these registers as event count ers, a one-pulse count oper ation is not possible. remark n = 0, 1 (3) setting compare register during timer count operation if the value to which the current value of 16-bit c apture/compare register n0 (crn0) has been changed is less than the value of 16-bit timer register n (tmn), tmn continues counting, overflows, and st arts counting again from 0. if the new value of crn0 (m) is less than the old value (n), the timer must be reset and restarted after the value of crn0 has been changed. figure 7-26. timing after changing compar e register during timer count operation x ? 1x nm ffffh 0000h 0001h 0002h count pulse tmn count value crn0 remarks 1. n > x > m 2. n = 0, 1
chapter 7 timer/counter function user?s manual u12768ej4v1ud 185 (4) data hold timing of capture register if the valid edge is input to the tin0 pin while 16-bit c apture/compare register n1 (crn1) is being read, crn1 performs a capture operation, but this capture value is not guaranteed. however, the interrupt request signal (inttmn1) is set as a result of detection of the valid edge. figure 7-27. data hold timing of capture register remark n = 0, 1 (5) setting valid edge before setting the valid edge of the tin0 pin, stop t he timer operation by resetting bits 2 and 3 (tmcn2 and tmcn3) of 16-bit timer mode control register n to 0, 0. set the valid edge by using bits 4 and 5 (esn00 and esn01) of prescaler mode register n (prmn). remark n = 0, 1 (6) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is being output, do not set osptn to 1. to output a one-shot pulse again, wait until the current one-shot pulse output is complete. (b) one-shot pulse output with external trigger if the external trigger occurs while a one- shot pulse is being output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output function of timer 0 or 1 via a software trigger, the tin0 pin cannot be used as a general-purpose port pin. remark n = 0, 1 tmn count value count pulse n + 1 n n + 2 m + 2 m + 1 m x n+1 a capture operation is performed but not guaranteed. edge input inttmn1 capture read signal crn1 interrupt value capture operation
chapter 7 timer/counter function user?s manual u12768ej4v1ud 186 (7) operation of ovfn flag (a) ovfn flag set the ovfn flag is set to 1 in the following case in addition to when the tmn register overflows: select the mode in which the timer is cl eared and started on a matc h between tmn and crn0. set the crn0 register to ffffh. when tmn is cleared from ffffh to 0000h on a match with the crn0 register. figure 7-28. operation timing of ovfn flag remark n = 0, 1 (b) clear ovfn flag even if the ovfn flag is cleared bef ore the next count clock is count ed (before tmn becomes 0001h) after tmn has overflowed, the ovfn flag is set again and the clear becomes invalid. remark n = 0, 1 (8) conflict operation (a) if the read period and cap ture trigger input conflict when 16-bit capture/compare register s n0 and n1 (crn0, crn1) are used as capture register s, if the read period and capture trigger input conf lict, the capture trigger has priori ty. the read data of the crn0 and crn1 registers is undefined. (b) if the match timing of th e write period and tmn conflict when 16-bit capture/compare regist ers n0 and n1 (crn0, crn1) are used as capture registers, because match detection cannot be performed correct ly if the match timing of the wr ite period and 16-bit timer register n (tmn) conflict, do not write to the crn0 and crn1 registers close to the match timing. remark n = 0, 1 (9) timer operation (a) crn1 capture even if 16-bit timer register n (tmn) is read, a capture to 16-bit capture/ compare register n1 (crn1) is not performed. count pulse crn0 0001h 0000h ffffh fffeh ffffh tmn ovfn inttmn0
chapter 7 timer/counter function user?s manual u12768ej4v1ud 187 (b) acknowledgement of tin0 and tin1 pins when the timer is stopped, input signal s to the tin0 and tin1 pins are not acknowledged, regardless of the cpu operation. (c) one-shot pulse output the one-shot pulse output oper ates correctly only in free-running mode or in clear & start mode at the valid edge of the tin0 pin. the one-shot pulse cannot be output in the clear & start mode on a match of tmn and crn0 because an overflow does not occur. remark n = 0, 1 (10) capture operation (a) if the valid edge of tin0 is specified for the count clock when the valid edge of tin0 is specifi ed for the count clock, the capture register with tin0 specified as a trigger will not operate correctly. (b) if both rising and falling edges are selected as th e valid edge of tin0, a capture operation is not performed. (c) to capture the signals corr ectly from tin0 and tin1 the capture trigger needs a pulse l onger than twice the count clock sele cted by prescaler mode registers n0 and n1 (prmn0, prmn1) in order to correct ly capture the signal s from tin1 and tin0. (d) interrupt request input although a capture operation is perfo rmed a the falling edge of the count clock, interrupt request inputs (inttmn0, inttmn1) are generated at the rising edge of the next count clock. remark n = 0, 1 (11) compare operation (a) when rewriting crn0 a nd crn1 during timer operation when rewriting 16-bit timer capture/co mpare registers n0 and n1 (crn0, crn1) , if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) when crn0 and crn1 ar e set to compare mode when crn0 and crn1 are set to compare mode, they do not perform a capture operat ion even if a capture trigger is input. remark n = 0, 1
chapter 7 timer/counter function user?s manual u12768ej4v1ud 188 (12) edge detection (a) when the tin0 or tin1 pin is hi gh level immediately after a system reset when the tin0 or tin1 pin is high leve l immediately after a system reset, if the valid edge of the tin0 or tin1 pin is specified as the rising edge or both rising and falling edges, and the oper ation of 16-bit timer/counter n (tmn) is then enabled, the rising edge will be detected immediately. care is therefore needed when the tin0 or tin1 pin is pulled up. howeve r, when operation is enabled after being stopped, the rising or falling edge is not detected. (b) sampling clock for noise elimination the sampling clock for noise elimination differs dependi ng on whether the tin0 valid edge is used as a count clock or a capture trigger. the former is sampled by f xx /2, and the latter is sampled by the count clock selected using prescaler mode register n0 or n1 (prm n0, prmn1). detecting t he valid edge can eliminate short pulse width noise because a capture operation is performed only after the valid edge is sampled and a valid level is detected twice. remark n = 0, 1
chapter 7 timer/counter function user?s manual u12768ej4v1ud 189 7.3 8-bit timers (tm2 to tm5) 7.3.1 outline ? 8-bit compare registers: 4 (crn0) can be used as 16-bit compare register s by connecting in cascade (2 max.). ? compare match/overflow interrupt request signal (inttmn) output enabled ? event input (tin) count enabled ? timer outputs that operate on ma tch detection: 1 each (ton) if using the p26/ti2/to2, p27/ti3/to 3, p36/ti4/to4, and p37/ ti5/to5 pins as the to 2 to to5 pins (timer outputs), set the value of ports 2 and 3 (p2, p3) to 0 (l ow-level output) and the value of the port 3 mode register (pm3) to 0 (port output mode). the logical sum (or) of the output value of the por t and the timer is output. since the ton pin and tin pin share a pin, one or other of these func tions (but not both) can be used. remark n = 2 to 5 7.3.2 functions 8-bit timer n has the following two modes (n = 2 to 5). mode using timer alone (individual mode) mode using cascade connection (16-bit resolution: cascade connection mode) caution when used without cascade connection, do not access to the fo llowing registers. ? 16-bit counters (tm23, tm45) 16-bit compare regi sters (cr23, cr45) the two modes are described next. (1) mode using timer alone (individual mode) the timer operates as an 8-bit timer/event counter. it can have the following functions. interval timer external event counter square wave output pwm output (2) mode using cascade connection (16-bi t resolution: cascade connection mode) the timer operates as a 16-bit time r/event counter by connecting tm2 and tm3 or tm4 and tm5 in cascade. it can have the following functions. interval timer with 16-bit resolution external event counter with 16-bit resolution square wave output with 16-bit resolution
chapter 7 timer/counter function user?s manual u12768ej4v1ud 190 figure 7-29. block diagram of tm2 to tm5 notes 1. the count clock is set by the tcln or tcln1 register. 2. serial interface clocks (tm2 and tm3 only) remarks 1. ? ] ? is a signal that can be directly connected to a port. 2. n = 2 to 5 7.3.3 configuration timers 2 to 5 consist of the following hardware. table 7-5. configuration of timers 2 to 5 item configuration timer registers 8-bit counter 2 to 5 (tm2 to tm5) 16-bit counter 23 and 45 (tm23, tm45) : only when connecting in cascade registers 8-bit compare register 2 to 5 (cr20 to cr50) 16-bit compare register 23 and 45 (cr23, cr45): only when connecting in cascade timer outputs to2 to to5 control registers timer clock se lect register 2 to 5, 21 to 51 (tcl2 to tcl5, tcl21 to tcl51) 8-bit timer mode control register 2 to 5 (tmc2 to tmc5) ovf clear match mask circuit selector selector selector tin count clock note 1 4 tcln3 selector internal bus timer mode control register n (tmcn) timer clock select register n, n1 (tcln, tcln1) invert level internal bus tcln2 tcln1 tcln0 tcen tmcn6 tmcn4 lvsn lvrn tmcn1 toen ton inttmn s r q inv s r q 8-bit counter n (tmn) 8-bit compare register n (crn0) note 2
chapter 7 timer/counter function user?s manual u12768ej4v1ud 191 (1) 8-bit counters 2 to 5 (tm2 to tm5) tmn is an 8-bit read-only register that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. through cascade connection, tm2 and tm3, and tm 4 and tm5 can be used as 16-bit timers. when using tmm and tmm + 1 in cascade as a 16-bit ti mer, the timer can be read using a 16-bit memory manipulation instruction. however, because these timers are connected by an internal 8-bit bus, tmm and tmm + 1 must be read twice. t herefore, read these timers twice and compare the values , bearing in mind that the reading occurs during a count change. when the count is read out dur ing operation, the count clo ck input temporarily stops and the count is read at that time. in the following cases, the count becomes 00h. (1) reset is input. (2) tcen is cleared. (3) tmn and crn0 match in the clear and start mode that occurs when tmn and crn0 match. caution when connected in cascade, these registers become 00h even when tcen in the lowest timer (tm2, tm4) is cleared. remark n = 2 to 5 m = 2, 4 (2) 8-bit compare register s 2 to 5 (cr20 to cr50) the crn0 register is set by an 8-bi t memory manipulation instruction. the value set in crn0 is always compared to the count val ue in 8-bit counter n (tmn). if the two values match, an interrupt request (inttmn) is generated (except in the pwm mode). the value of crn0 can be set in the range of 00h to ffh, and can be written during counting. when using tmm and tmm + 1 in cascade as a 16-bit timer, crm0 and cr (m + 1) 0 operate as a 16-bit compare register that is set by a 16- bit memory manipulation instruction. the counter and regi ster values are compared in 16-bit lengths, and if they match, an interrupt request (inttmm) is generated. bec ause the interrupt request inttmm + 1 is also generated at this time, be sure to mask interrupt request inttmm + 1 when using tmm and tmm + 1 in cascade connection. reset input sets these registers to 00h. caution if data is set in a cascade connect ion, always set after stopping the timer. remark n = 2 to 5 m = 2, 4
chapter 7 timer/counter function user?s manual u12768ej4v1ud 192 7.3.4 timer n control register the following two types of r egisters control timer n. timer clock select registers n and n1 (tcln, tcln1) 8-bit timer mode control register n (tmcn)
chapter 7 timer/counter function user?s manual u12768ej4v1ud 193 (1) timer clock select register s 2 to 5, 21 to 51 (tcl2 to tcl5 and tcl21 to tcl51) these registers set the count clock of timer n. tcln and tcln1 are set by an 8-bit me mory manipulation instruction. reset input sets these registers to 00h. remark n = 2 to 5 (1/2) after reset: 00h r/w address: fffff244h, fffff254h 7 6 5 4 3 2 1 0 tcln 0 0 0 0 0 tcln2 tcln1 tcln0 (n = 2, 3) after reset: 00h r/w address: fffff24eh, fffff25eh 7 6 5 4 3 2 1 0 tcln1 0 0 0 0 0 0 0 tcln3 (n = 2, 3) count clock selection f xx tcln3 tcln2 tcln1 tcln0 count clock 20 mhz 17 mhz 10 mhz 2 mhz 0 0 0 0 tin falling edge ? ? ? ? 0 0 0 1 tin rising edge ? ? ? ? 0 0 1 0 f xx /4 200 ns 235 ns 400 ns 2 s 0 0 1 1 f xx /8 400 ns 471 ns 800 ns 4 s 0 1 0 0 f xx /16 800 ns 941 ns 1.6 s 8 s 0 1 0 1 f xx /32 1.6 s 1.9 s 3.2 s 16 s 0 1 1 0 f xx /128 6.4 s 7.5 s 12.8 s 64 s 0 1 1 1 f xx /512 25.6 s 30.1 s 51.2 s 256 s 1 0 0 0 setting prohibited ? ? ? ? 1 0 0 1 setting prohibited ? ? ? ? 1 0 1 0 f xx /64 3.2 s 3.8 s 6.4 s 32 s 1 0 1 1 f xx /256 12.8 s 15.1 s 25.6 s 128 s 1 1 0 0 setting prohibited ? ? ? ? 1 1 0 1 setting prohibited ? ? ? ? 1 1 1 0 setting prohibited ? ? ? ? 1 1 1 1 setting prohibited ? ? ? ? cautions 1. when tcln and tcln1 are overwritten by different data , write after temporarily stopping the timer. 2. always set bits 3 to 7 of tcln and bits 1 to 7 of tcln1 to 0. remark when connected in cascade, the settings of tcl33 to tcl30 of tm3 are invalid.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 194 (2/2) after reset: 00h r/w address: fffff264h, fffff274h 7 6 5 4 3 2 1 0 tcln 0 0 0 0 0 tcln2 tcln1 tcln0 (n = 4, 5) after reset: 00h r/w address: fffff26eh, fffff27eh 7 6 5 4 3 2 1 0 tcln1 0 0 0 0 0 0 0 tcln3 (n = 4, 5) count clock selection f xx tcln3 tcln2 tcln1 tcln0 count clock 20 mhz 17 mhz 10 mhz 2 mhz 0 0 0 0 tin falling edge ? ? ? ? 0 0 0 1 tin rising edge ? ? ? ? 0 0 1 0 f xx /4 200 ns 235 ns 400 ns 2 s 0 0 1 1 f xx /8 400 ns 471 ns 800 ns 4 s 0 1 0 0 f xx /16 800 ns 941 ns 1.6 s 8 s 0 1 0 1 f xx /32 1.6 s 1.9 s 3.2 s 16 s 0 1 1 0 f xx /128 6.4 s 7.5 s 12.8 s 64 s 0 1 1 1 f xt (subclock) 30.5 s 30.5 s 30.5 s 30.5 s 1 0 0 0 setting prohibited ? ? ? ? 1 0 0 1 setting prohibited ? ? ? ? 1 0 1 0 f xx /64 3.2 s 3.8 s 6.4 s 32 s 1 0 1 1 f xx /256 12.8 s 15.1 s 25.6 s 128 s 1 1 0 0 setting prohibited ? ? ? ? 1 1 0 1 setting prohibited ? ? ? ? 1 1 1 0 setting prohibited ? ? ? ? 1 1 1 1 setting prohibited ? ? ? ? cautions 1. when tcln and tcln1 are overwritten by different data , write after temporarily stopping the timer. 2. always set bits 3 to 7 of tcln and bits 1 to 7 of tcln1 to 0. remark when connected in cascade, the settings of tcl53 to tcl50 of tm5 are invalid.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 195 (2) 8-bit timer mode control re gisters 2 to 5 (tmc2 to tmc5) the tmcn register makes the following six settings. (1) controls counting by 8-bit counter n (tmn) (2) selects the operating mode of 8-bit counter n (tmn) (3) selects the individual mode or cascade connection mode (4) sets the state of t he timer output flip-flop (5) controls the timer flip-flop or selects t he active level in the pwm (free-running) mode (6) controls timer output tmcn is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 04h (the hardware status is initializ ed to 04h, but 00h is read when read).
chapter 7 timer/counter function user?s manual u12768ej4v1ud 196 after reset: 04h r/w address: tmc2 fffff246h tmc4 fffff266h tmc3 fffff256h tmc5 fffff276h 7 6 5 4 3 2 1 0 tmcn tcen tmcn6 0 tmcn4 lvsn lvrn tmcn1 toen (n = 2 to 5) tcen tmn count operation control 0 counting is disabled after the counter is cleared to 0 (prescaler disabled) 1 start count operation tmcn6 tmn operating mode selection 0 clear and start mode when tmn and crn0 match 1 pwm (free-running) mode tmcn4 individual mode or ca scade connection mode selection 0 individual mode (fixed to 0 when n = 2, 4) 1 cascade connection mode (connection to lower timer) lvsn lvrn setting state of timer output flip-flop 0 0 not change 0 1 reset timer output flip-flop to 0 1 0 set timer output flip-flop to 1 1 1 setting prohibited other than pwm (free-running) mode (tmcn6 = 0) pwm (free-running) mode (tmcn6 = 1) tmcn1 control of timer f/f selection of active level 0 disable inversion operation active high 1 enable inversion operation active low toen timer output control 0 disable output (port mode) 1 enable output caution stop the timer operati on temporarily to rewrite the tmcn4 and tmcn6 bits. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tcen = 0. 2. if the lvsn and lvrn bits are read after setting data, 0 is read.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 197 7.4 8-bit timer operation 7.4.1 operation as interval timer (8-bit operation) the timer operates as an interval timer that repeatedly generates inte rrupts at the interval of the count preset by 8-bit compare register n (crn0). if the count in 8-bit counter n (tmn ) matches the value set in crn0, t he value of tmn is cleared to 0 and continues counting. at the same time, an interrupt request signal (inttmn) is generated. the tmn count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of time r clock select register n (tcln) and by bit 0 (tcln3) of timer clock select register n1 (tcln1) (n = 2 to 5). setting method (1) set each register. tcln, tcln1: select the count clock. crn0: compare value tmcn: selects the clear and st art mode when tmn and crn0 match. (tmcn = 0000xxx0b, x is don?t care) (2) when tcen = 1 is set, counting starts. (3) when the values of tmn and crn0 match, inttmn is generated (tmn is cleared to 00h). (4) then, inttmn is repeatedly generat ed at the same interval. when counting stops, set tcen = 0. figure 7-30. timing of interval timer operation (1/3) basic operation remarks 1. interval time = (n + 1) t; n = 00h to ffh 2. n = 2 to 5 t 00h n 01h 01h 00h n n n n n n count start 01h 00h crn0 ton tcen inttmn clear clear interrupt acknowledgement interrupt acknowledgement interval time interval time interval time
chapter 7 timer/counter function user?s manual u12768ej4v1ud 198 figure 7-30. timing of interval timer operation (2/3) when crn0 = 00h remark n = 2 to 5 when crn0 = ffh remark n = 2 to 5 t 00h 00h 00h 00h 00h tmn count clock interval time crn0 tcen inttmn ton t 01h feh ffh 00h feh ffh 00h ffh ffh ffh tmn crn0 tcen inttmn ton interrupt acknowledgement interval time count clock interrupt acknowledgement
chapter 7 timer/counter function user?s manual u12768ej4v1ud 199 figure 7-30. timing of interval timer operation (3/3) operated by crn0 transition (m < n) remark n = 2 to 5 operated by crn0 transition (m > n) remark n = 2 to 5 00h crn0 transition tmn overflows since m < n 00h mm n ffh 00h nm tmn count clock crn0 tcen inttmn ton t n ? 1 01h 00h 00h m n nm ? 1 01h nm tmn count clock crn0 transition crn0 tcen inttmn ton t
chapter 7 timer/counter function user?s manual u12768ej4v1ud 200 7.4.2 operation as external event counter the external event counter count s the number of external clock pulses that are input to tin. each time a valid edge specified by timer clock select r egister n, n1 (tcln, tcln1) is input, tmn is incremented. the edge setting can be selected as ei ther the rising or falling edge. if the total of tmn and the value of 8-bit compare regist er n (crn0) match, tmn is cleared to 0 and an interrupt request signal (inttmn) is generated. inttmn is generated each time the tm n value matches the crn0 value. remark n = 2 to 5 figure 7-31. timing of external event c ounter operation (when rising edge is set) 00 01 02 03 04 05 n ? 1n n 00 01 02 03 tin crn0 tmn count value inttmn remark n = 2 to 5
chapter 7 timer/counter function user?s manual u12768ej4v1ud 201 7.4.3 operation as square wave output (8-bit resolution) a square wave with any frequency is out put at the interval preset by 8-bit compare register n (crn0). by setting bit 0 (toen) of 8-bit timer mode control register n (tmcn) to 1, the output state of ton is inverted with the count preset in crn0 as the interv al. therefore, a square wave output with any frequency (duty factor = 50%) is possible. setting method (1) set the registers. set the port latch and port mode register to 0 tcln, tcln1: select the count clock crn0: compare value tmcn: clear and start mode entered when tmn and crn0 match lvsn lvrn setting state of timer output flip-flop 1 0 high-level output 0 1 low-level output inversion of timer output flip-flop enabled timer output enabled toen = 1 (2) when tcen = 1 is set, the counter starts operating. (3) if the values of tmn and crn0 match, the timer out put flip-flop inverts. also, inttmn is generated and tmn is cleared to 00h. (4) then, the timer output flip-flop is inverted at the same interval to output a square wave from ton. figure 7-32. timing of square wave output operation note the initial value of the to n output is set by bits 2 and 3 (lvrn, lvsn ) of 8-bit timer mode control register n (tmcn). remarks 1. square-wave output frequency = 1/2t (n + 1) 2. n = 2 to 5 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h crn0 ton note count clock tmn count value count start t
chapter 7 timer/counter function user?s manual u12768ej4v1ud 202 7.4.4 operation as 8-bit pwm output by setting bit 6 (tmcn6) of 8-bit timer mode control regist er n (tmcn) to 1, the timer operates as a pwm output. pulses with the duty factor determined by the value set to 8-bit compare regi ster n (crn0) are output from ton. set the width of the active level of the pwm pulse to cr n0. the active level can be se lected by bit 1 (tmcn1) of tmcn. the count clock can be selected by bits 0 to 2 (tcln0 to tc ln2) of timer clock select register n (tcln) and by bit 0 (tcln3) of timer clock select register n1 (tcln1). the pwm output can be enabled and disabl ed by bit 0 (toen) of tmcn. caution crn0 can be rewritten only once in one cycle while in the pwm mode. remark n = 2 to 5 (1) basic operation of the pwm output setting method (1) set the port latch and port mode register n to 0. (2) set the active level width in 8-bit compare register n (crn0). (3) select the count clock using timer cl ock select register n, n1 (tcln, tcln1). (4) set the active level in bit 1 (tmcn1) of tmcn. (5) if bit 7 (tcen) of tmcn is set to 1, count ing starts. when counting stops, set tcen to 0. pwm output operation (1) when counting starts, the pwm out put (output from ton) outputs the inactive level until an overflow occurs. (2) when the overflow occurs, the active level specified in step (1) in the setting method is output. the active level is output until crn0 and the count of 8-bit counter n (tmn) match. (3) the pwm output after crn0 and the count match is the inactive level until an overflow occurs again. (4) steps (2) and (3) repeat until counting stops. (5) if counting is stopped by tcen = 0, the pwm output goes to the inactive level. remark n = 2 to 5
chapter 7 timer/counter function user?s manual u12768ej4v1ud 203 (a) basic operation of pwm output figure 7-33. timing of pwm output basic operation (active level = h) when crn0 = 00h when crn0 = ffh remarks 1. pwm frequency = 1/2 8 t duty = n/2 8 2. n = 2 to 5 0 0 h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h tmn crn0 count clock active level active level active level tcen inttmn ton t count clock tmn crn0 tcen inttmn ton inactive level inactive level 00h 01h ffh 00h 01h 02h n n+1 n+2 ffh 00h 01h 02h m 00h 00h t count clock tmn crn0 tcen inttmn ton inactive level inactive level active level active level inactive level 00h 01h ffh 00h 01h 02h n n+1 n+2 ffh 00h 01h 02h m 00h ffh t
chapter 7 timer/counter function user?s manual u12768ej4v1ud 204 (b) operation based on crn0 transitions figure 7-34. timing of operation based on crn0 transition when the crn0 value changes from n to m before tmn overflows when the crn0 value changes from n to m after tmn overflows when the crn0 value changes from n to m during tw o clocks (00h, 01h) immediat ely after tmn overflows remark n = 2 to 5 inttmn ffh ffh 00h 01h 02h 00h 01h 02h n n + 2 n + 1 tmn crn0 tcen ton count clock crn0 transition (n m) m+1 m+2 mm+1m+2 m n m h inttmn tmn crn0 tcen ton count clock crn0 transition (n m) h nm n ffh ffh 00h 01h 02h 00h 01h 02h n n + 2 n + 1 n+ 1 n+2 nm+1m+2 m 03h inttmn tmn crn0 tcen ton count clock crn0 transition (n m) h nm n ffh ffh 00h 01h 02h 00h 01h 02h n n + 2 n + 1 n+ 1 n+2 nm+1m+2 m 03h
chapter 7 timer/counter function user?s manual u12768ej4v1ud 205 7.4.5 operation as inter val timer (16 bits) (1) cascade connection (16-bit timer) mode the v850/sa1 provides 16-bit registers that can be used onl y when connected in cascade. the following registers are available. tm2 to tm3 cascade connection: 16-bit counter tm23 (address: fffff24ah) 16-bit compare register cr23 (address: fffff24ch) tm4 to tm5 cascade connection: 16-bit counter tm45 (address: fffff26ah) 16-bit compare register cr45 (address: fffff26ch) by setting bit 4 (tmcm4) of 8-bit timer mode control regi ster m (tmcm) to 1, the ti mer enters the timer/counter mode with 16-bit resolution (m = 3, 5). the timer operates as an interval time r by repeatedly generating interrupts (n = 2 to 5) with the c ount preset in 8- bit compare register n (crn0) as the interval. the following is an explanation of how to use tm2 and tm3. substitute tm4 and tm5 for tm2 and tm3 as appropriate when using tm4 and tm5. example of setting method (when tm2 and tm3 are connected in cascade) <1> set each register. ? tcl20, tcl21: select the count clock for tm2 (t m3 does not need to be set in a cascade connection) ? cr20, cr30: compare values (each compare value can be set from 00h to ffh) ? tmc2: selects clear and start mode when tm2 and cr20 match (x: don?t care) tm2 tmc2 = 0000xxx0b tm3 tmc3 = 0001xxx0b <2> start the count operation by first setting the tce3 bit of tmc3 to 1, and then setting the tce2 bit of tmc2 to 1. <3> if a match occurs between cascade-connected ti mer tm2 and cr20, the in ttm2 of tm2 will be generated (tm2 and tm3 are cleared to 00h). <4> imttm2 will then be generated repeat edly at the same interval. cautions 1. to change the set value of the compare register (cr23) while the 8-bit timers (tm2, tm3) are connected in cascade and be ing used as a 16-bit timer (t m23), change the cr23 value after stopping the count operation of each of the 8-bit timers connected in cascade. if the cr23 value is changed without stopping the time rs, the value of the higher 8 bits (tm3) will be undefined. 2. if the count value of the higher timer (tm3 ) matches cr30, the higher timer (tm3) interrupt request (inttm3) will be generated, even wh en the timers are be ing used in a cascade connection. tm3 must therefore alw ays be masked to disable interrupts. 3. set the tce3 bit of tmc3 be fore setting the tce2 bit of tmc2. 4. restarting and stopping the count is possible ju st by setting the tce2 bit of tmc2 to 1 or 0 respectively.
chapter 7 timer/counter function user?s manual u12768ej4v1ud 206 the following shows a timing example of the cascade connection mode with 16-bit resolution. figure 7-35. cascade connection mode with 16-bit resolution n+1 n 00h 01h tm2 count clock enable operation starting count ffh n 01h 00h 01h 00h ffh 00h ffh 00h 00h a 00h tm3 01h 02h m m ? 1 00h 00h b cr20 n cr30 m tce2 tce3 inttm2 to2 interval time operation stopped interrupt generation level inverted counter cleared
chapter 7 timer/counter function user?s manual u12768ej4v1ud 207 7.4.6 cautions (1) error when timer starts an error of up to 1 clock occurs in the time until the ma tch signal is generated after the timer starts. the reason is that 8-bit counter n (tmn) starts asynchronously to the count pulse. figure 7-36. start timing of timer n 00h 01h 02h 03h 04h timer starts tmn count value count pulse remark n = 2 to 5 (2) operation after compare register is changed while timer is counting if the value after 8-bit compare register n (crn0) changes is less than the value of the 8- bit timer register (tmn), counting continues, overflows, and st arts again from 0. consequently, w hen the value after crn0 changes (m) is less than the value before the change (n) and less than the count value of the tm n register, the timer must restart after crn0 changes (n = 2 to 5). figure 7-37. timing after compare regist er changes during timer count operation tmn count value n count pulse crn0 x ? 1 x ffh 00h 01h 02h m remarks 1. n > x > m 2. n = 2 to 5 caution except when the tin input is selected, a lways set tcen = 0 before setting the stop state. (3) tmn read out during timer operation since reading out tmn during operation o ccurs while the selected clock is te mporarily stopped, se lect a high- or low-level waveform that is longer t han the selected clock (n = 2 to 5).
user?s manual u12768ej4v1ud 208 chapter 8 watch timer 8.1 functions the watch timer has the following functions. watch timer interval timer the watch timer and interval timer functions can be used at the same time. the block diagram of the watch timer is shown below. figure 8-1. block diagram of watch timer f xt f w f xx /2 9 f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 9 intwt intwti wtm7 wtm6 wtm5 wtm4 wtm3 wtm1 wtm0 internal bus selector selector selector clear 9-bit prescaler 5-bit counter clear watch timer mode control register (wtm) caution the value of the 5-bit count er cannot be read or written. remark f xx : main clock frequency f xt : subclock frequency f w : watch timer clock frequency
chapter 8 watch timer user?s manual u12768ej4v1ud 209 (1) watch timer the watch timer generates an interrupt r equest signal (intwt) at time intervals of 0.5 seconds by using the main clock or subclock. (2) interval timer the watch timer generates an interr upt request (intwti) at time in tervals specified in advance. table 8-1. interval time of interval timer interval time f w = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms remark f w : watch timer clock frequency 8.2 configuration the watch timer consists of the following hardware. table 8-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
chapter 8 watch timer user?s manual u12768ej4v1ud 210 8.3 watch timer control register the watch timer mode control register (wtm) controls the watch timer. (1) watch timer mode c ontrol register (wtm) this register enables or disables the count clock and operation of the watch time r, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the inte rrupt time of the watch timer. wtnm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears wtm to 00h. after reset: 00h r/w address: fffff360h 7 6 5 4 3 2 1 0 wtm wtm7 wtm6 wtm5 wtm4 wtm3 0 wtm1 wtm0 wtm7 selection of counter clock of watch timer 0 f xx /2 9 (main clock) 1 f xt (subclock) wtm6 wtm5 wtm4 selection of interval time of prescaler 0 0 0 2 4 /f w (488 s) 0 0 1 2 5 /f w (977 s) 0 1 0 2 6 /f w (1.95 ms) 0 1 1 2 7 /f w (3.91 ms) 1 0 0 2 8 /f w (7.81 ms) 1 0 1 2 9 /f w (15.6 ms) other than above setting prohibited wtm3 selection of interrupt time of watch timer 0 2 14 /f w (0.5 s) 1 2 5 /f w (977 s) wtm1 control of operation of 5-bit counter 0 clears after operation stops 1 starts wtm0 watch timer operation enable 0 operation stopped (enabled both prescaler and timer cleared) 1 operation remarks 1. f w : watch timer clock frequency (f xx /2 9 or f xt ) 2. values in parentheses apply when f w = 32.768 khz.
chapter 8 watch timer user?s manual u12768ej4v1ud 211 8.4 operation 8.4.1 operation as watch timer the watch timer operates at time intervals of 0.5 sec onds with the subclock (32.768 kh z) or main clock (16.777 mhz). the watch timer generates an interrupt request at fixed time intervals. the count operation of the watch timer is started when bits 0 (w tm0) and 1 (wtm1) of the watch timer mode control register (wtm) are set to 1. when these bits are cleared to 0, t he 9-bit prescaler and 5-bit counter are cleared, and the watch timer stops the count operation. the watch timer clears the 5-bit counter by setting the wtm1 bit to 0. at this time, an error of up to 15.6 ms may occur. the interval timer can be cleared by setting the wtm0 bit to 0. however, because the 5-bit counter is cleared at the same time, an error of up to 0.5 seconds ma y occur when the watch timer overflows (intwt). 8.4.2 operation as interval timer the watch timer can also be used as an interval timer t hat repeatedly generates an interr upt at intervals specified by a count value set in advance. the interval time can be selected by bits 4 through 6 (wtm4 through wtm6) of the watch timer mode control register (wtm). table 8-3. interval time of interval timer wtm6 wtm5 wtm4 interval time f w = 32.768 khz 0 0 0 2 4 1/f w 488 s 0 0 1 2 5 1/f w 977 s 0 1 0 2 6 1/f w 1.95 ms 0 1 1 2 7 1/f w 3.91 ms 1 0 0 2 8 1/f w 7.81 ms 1 0 1 2 9 1/f w 15.6 ms other than above setting prohibited remark f w : watch timer clock frequency
chapter 8 watch timer user?s manual u12768ej4v1ud 212 figure 8-2. operation timing of watch timer/interval timer start 5-bit counter overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti nt nt remark f w : watch timer clock frequency ( ): f w = 32.768 khz n: interval timer operation count 8.4.3 cautions some time is required before the first watch timer in terrupt request (intwt) is gener ated after operation is enabled (wtm1 and wtm0 bits of watch timer mode control register (wtm) = 1, 1). figure 8-3. example of generation of watch timer interrupt request (int wt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32.768 = 0.015625 s). intwt is then generated every 0.5 seconds. 0.515625 s 0.5 s 0.5 s wtm0 = 1 wtm1 = 1 intwt
user?s manual u12768ej4v1ud 213 chapter 9 watchdog timer 9.1 functions the watchdog timer has the following functions. figure 9-1 shows a block diagram of the watchdog timer. watchdog timer interval timer selecting the oscillation stabilization time caution use the watchdog timer mode register (wdtm) to select the watc hdog timer mode or the interval timer mode. figure 9-1. block diagram of watchdog timer f xx / 2 10 f xx / 2 22 f xx / 2 20 f xx / 2 19 f xx / 2 18 f xx / 2 17 f xx / 2 16 f xx / 2 15 f xx / 2 14 run osc wdcs2 wdcs1 wdcs0 osts2 osts1 osts0 run wdcs osts wdtm wdtm4 3 3 internal bus clear prescaler selector selector output controller intwdt note 1 intwdtm note 2 notes 1. in watchdog timer mode 2. in interval timer mode remark f xx : main clock frequency
chapter 9 watchdog timer user?s manual u12768ej4v1ud 214 (1) watchdog timer mode this mode detects a program loop. when a loop is detected, a non-maskable interrupt can be generated. table 9-1. loop detection time of watchdog timer loop detection time clock f xx = 20 mhz f xx = 17 mhz f xx = 10 mhz f xx = 2 mhz 2 14 /f xx 819.2 s 964 s 1.6 ms 8.2 ms 2 15 /f xx 1.6 ms 1.928 ms 3.2 ms 16.4 ms 2 16 /f xx 3.3 ms 3.855 ms 6.6 ms 32.8 ms 2 17 /f xx 6.6 ms 7.710 ms 13.1 ms 65.5 ms 2 18 /f xx 13.1 ms 15.42 ms 26.2 ms 131.1 ms 2 19 /f xx 26.2 ms 30.84 ms 52.4 ms 262.1 ms 2 20 /f xx 52.4 ms 61.68 ms 104.9 ms 524.3 ms 2 22 /f xx 209.7 ms 246.7 ms 419.4 ms 2.1 s (2) interval timer mode interrupts are generated at a preset time interval. table 9-2. interval time of interval timer interval time clock f xx = 20 mhz f xx = 17 mhz f xx = 10 mhz f xx = 2 mhz 2 14 /f xx 819.2 s 964 s 1.6 ms 8.2 ms 2 15 /f xx 1.6 ms 1.928 ms 3.2 ms 16.4 ms 2 16 /f xx 3.3 ms 3.855 ms 6.6 ms 32.8 ms 2 17 /f xx 6.6 ms 7.710 ms 13.1 ms 65.5 ms 2 18 /f xx 13.1 ms 15.42 ms 26.2 ms 131.1 ms 2 19 /f xx 26.2 ms 30.84 ms 52.4 ms 262.1 ms 2 20 /f xx 52.4 ms 61.68 ms 104.9 ms 524.3 ms 2 22 /f xx 209.7 ms 246.7 ms 419.4 ms 2.1 s
chapter 9 watchdog timer user?s manual u12768ej4v1ud 215 9.2 configuration the watchdog timer consists of the following hardware. table 9-3. watchdog timer configuration item configuration control registers oscillation stabilization time select register (osts) watchdog timer clock sele ct register (wdcs) watchdog timer mode register (wdtm) 9.3 watchdog timer control register three registers control the watchdog timer. oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) (1) oscillation stabilization time select register (osts) this register selects the oscillation stabilization time after a reset is applied or the software stop mode is released until the oscillation is stable. osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. after reset: 04h r/w address: fffff380h 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 20 mhz 17 mhz 10 mhz 2 mhz 0 0 0 2 14 /f xx 819 s 964 s 1.6 ms 8.2 ms 0 0 1 2 16 /f xx 3.3 ms 3.855 ms 6.6 ms 32.8 ms 0 1 0 2 17 /f xx 6.6 ms 7.710 ms 13.1 ms 65.5 ms 0 1 1 2 18 /f xx 13.1 ms 15.42 ms 26.2 ms 131.1 ms 1 0 0 2 19 /f xx (after reset) 26.2 ms 30.84 ms 52.4 ms 262.1 ms other than above setting prohibited
chapter 9 watchdog timer user?s manual u12768ej4v1ud 216 (2) watchdog timer clock select register (wdcs) this register selects the overflow time of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. after reset: 00h r/w address: fffff382h 7 6 5 4 3 2 1 0 wdcs 0 0 0 0 0 wdcs2 wdcs1 wdcs0 watchdog timer/interval timer overflow time f xx wdcs2 wdcs1 wdcs0 clock 20 mhz 17 mhz 10 mhz 2 mhz 0 0 0 2 14 /f xx 819.2 s 964 s 1.6 ms 8.2 ms 0 0 1 2 15 /f xx 1.6 ms 1.928 ms 3.2 ms 16.4 ms 0 1 0 2 16 /f xx 3.3 ms 3.855 ms 6.6 ms 32.8 ms 0 1 1 2 17 /f xx 6.6 ms 7.710 ms 13.1 ms 65.5 ms 1 0 0 2 18 /f xx 13.1 ms 15.42 ms 26.2 ms 131.1 ms 1 0 1 2 19 /f xx 26.2 ms 30.84 ms 52.4 ms 262.1 ms 1 1 0 2 20 /f xx 52.4 ms 61.68 ms 104.9 ms 524.3 ms 1 1 1 2 22 /f xx 209.7 ms 246.7 ms 419.4 ms 2.1 s caution be sure to set bits 3 to 7 to 0.
chapter 9 watchdog timer user?s manual u12768ej4v1ud 217 (3) watchdog timer mode register (wdtm) this register sets the operat ing mode of the watchdog timer, and enables and disables counting. wdtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. after reset: 00h r/w address: fffff384h 7 6 5 4 3 2 1 0 wdtm run 0 0 wdtm4 0 0 0 0 run operating mode selection for watchdog timer note 1 0 disable count 1 clear count and start counting wdtm4 operating mode selection for watchdog timer note 2 0 interval timer mode (if an overflow occurs, the maskabl e interrupt intwdtm is generated.) 1 watchdog timer mode 1 (if an overflow occurs, the non-mask able interrupt intwdt is generated.) notes 1. once run is set (1), the register cannot be cl eared (0) by software. therefore, when counting starts, counting cannot be st opped except by reset input. 2. once wdtm4 is set (1), the regist er cannot be cleared (0) by software. caution if run is set (1) and the watchdog timer is cleared, the actua l overflow time can be up to 2 10 /f xx [seconds] shorter than the set time.
chapter 9 watchdog timer user?s manual u12768ej4v1ud 218 9.4 operation 9.4.1 operating as watchdog timer set bit 4 (wdtm4) of the watchdog timer mode register (wdtm) to 1 to operate as a watchdog timer to detect a program loop. setting bit 7 (run) of wdtm to 1 starts the count operation. a fter counting starts, if run is set to 1 again within the set time interval for loop detection, the watchdog timer is cleared and counting starts again. if run is not set to 1 and the loop detection time has elapsed, a non-maskable interr upt (intwdt) is generated (no reset function). the watchdog timer stops running in the idle mode and software stop mode. consequently, set run to 1 and clear the watchdog timer before entering the idle mode or software stop m ode. do not set the watchdog timer when operating in the halt mode since t he watchdog timer runs in halt mode. cautions 1. the actual loop de tection time can be up to 2 10 /f xx [seconds] shorter than the set time. 2. when the subclock is sel ected as the cpu clo ck, the watchdog timer stops (suspends) counting. table 9-4. loop detection time of watchdog timer loop detection time clock f xx = 20 mhz f xx = 17 mhz f xx = 10 mhz f xx = 2 mhz 2 14 /f xx 819.2 s 964 s 1.6 ms 8.2 ms 2 15 /f xx 1.6 ms 1.928 ms 3.2 ms 16.4 ms 2 16 /f xx 3.3 ms 3.855 ms 6.6 ms 32.8 ms 2 17 /f xx 6.6 ms 7.710 ms 13.1 ms 65.5 ms 2 18 /f xx 13.1 ms 15.42 ms 26.2 ms 131.1 ms 2 19 /f xx 26.2 ms 30.84 ms 52.4 ms 262.1 ms 2 20 /f xx 52.4 ms 61.68 ms 104.9 ms 524.3 ms 2 22 /f xx 209.7 ms 246.7 ms 419.4 ms 2.1 s
chapter 9 watchdog timer user?s manual u12768ej4v1ud 219 9.4.2 operating as interval timer set bit 4 (wdtm4) to 0 in the watchdog timer mode regist er (wdtm) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. when operating as an interval timer, the interrupt mask flag (wdtmk) of the wdtic register and the priority setting flag (wdtpr0 to wdtpr2) become valid, and a maskable interrupt (intwd tm) can be generated. the default priority of intwdtm has the highest pr iority setting of the maskable interrupts. the interval timer continues operati ng in the halt mode and st ops in the idle mode and software stop mode. therefore, before ent ering the idle mode/software stop mode, set t he run bit of wdtm register to 1 and clear the interval timer. then set the idle mode/software stop mode. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (selecting the watchdog timer mode), the interval timer mode is not entered as long as reset is not input. 2. the interval time immediately after setting in wdtm can be up to 2 10 /f xx [seconds] shorter than the set time. 3. when the subclock is selected as the cpu cl ock, the watchdog time r stops (suspends) counting. table 9-5. interval time of interval timer interval time clock f xx = 20 mhz f xx = 17 mhz f xx = 10 mhz f xx = 2 mhz 2 14 /f xx 819.2 s 964 s 1.6 ms 8.2 ms 2 15 /f xx 1.6 ms 1.928 ms 3.2 ms 16.4 ms 2 16 /f xx 3.3 ms 3.855 ms 6.6 ms 32.8 ms 2 17 /f xx 6.6 ms 7.710 ms 13.1 ms 65.5 ms 2 18 /f xx 13.1 ms 15.42 ms 26.2 ms 131.1 ms 2 19 /f xx 26.2 ms 30.84 ms 52.4 ms 262.1 ms 2 20 /f xx 52.4 ms 61.68 ms 104.9 ms 524.3 ms 2 22 /f xx 209.7 ms 246.7 ms 419.4 ms 2.1 s
chapter 9 watchdog timer user?s manual u12768ej4v1ud 220 9.5 standby function control register (1) oscillation stabilization time select register (osts) the wait time from releasing the so ftware stop mode until the oscillation stab ilizes is controlled by the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. after reset: 04h r/w address: fffff380h 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 20 mhz 17 mhz 10 mhz 2 mhz 0 0 0 2 14 /f xx 819.2 s 964 s 1.6 ms 8.2 ms 0 0 1 2 16 /f xx 3.3 ms 3.855 ms 6.6 ms 32.8 ms 0 1 0 2 17 /f xx 6.6 ms 7.710 ms 13.1 ms 65.5 ms 0 1 1 2 18 /f xx 13.1 ms 15.42 ms 26.2 ms 131.1 ms 1 0 0 2 19 /f xx (after reset) 26.2 ms 30.84 ms 52.4 ms 262.1 ms other than above setting prohibited caution the wait time at the rel ease of the software stop mode does not include the time (?a? in the figure below) until clock oscillation starts afte r releasing the software st op mode when reset is input or an inte rrupt is generated. v ss software stop mode release a voltage waveform at x1 pin
user?s manual u12768ej4v1ud 221 chapter 10 serial interface function 10.1 overview the v850/sa1 supports the followi ng on-chip serial interfaces. channel 0: 3-wire serial i/o (csi0)/i 2 c bus interface (i 2 c) note channel 1: 3-wire serial i/o (csi1)/a synchronous serial interface (uart0) channel 2: 3-wire serial i/o (csi2) channel 3: asynchronous serial interface (uart1) note i 2 c supports multi-masters ( pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only). either 3-wire serial i/o or i 2 c can be used as a serial interface. 10.2 3-wire serial i/o (csi0 to csi2) csin (n = 0 to 2) has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. (2) 3-wire serial i/o mode (fixed to msb first) this is an 8-bit data transfer mode using three lines: a seri al clock line (sckn), serial output line (son), and serial input line (sin). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in the 8-bit data in serial transfers is fixed to the msb. the sckn and son pins are set to normal output or n-ch open-drain output by setting t he port 1 function register (pf1) and port 2 function register (pf2). 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clocked serial interface, a display controller, etc.
chapter 10 serial interface function user?s manual u12768ej4v1ud 222 10.2.1 configuration csin consists of the following hardware. table 10-1. configuration of csin item configuration registers serial i/o shift regi sters 0 to 2 (sio0 to sio2) control registers serial clock select registers 0 to 2 (csis0 to csis2) serial operation mode registers 0 to 2 (csim0 to csim2) figure 10-1. block diagra m of 3-wire serial i/o tmx output clock selection sckn son sin intcsin internal bus selector 8 serial clock controller serial clock counter serial i/o shift register n (sion) interrupt generator remark n = 0 to 2 remarks 1. n = 0 to 2 2. tmx output is as follows: when n = 0: tm2 when n = 1, 2: tm3 (1) serial i/o shift registers 0 to 2 (sio0 to sio2) sion is an 8-bit register that performs parallel-se rial conversion and serial transmission/reception (shift operations) synchronized with the serial clock. sion is set by an 8-bit memory manipulation instruction. when ?1? is set to bit 7 (csien) of serial operation mode register n (csimn), a serial operation can be started by writing data to or reading data from sion. when transmitting, data written to sion is output via the serial output (son). when receiving, data is read from the se rial input (sin) and written to sion. reset input resets these registers to 00h. caution do not execute sion accesses except for accesses that become the transfer start trigger during a transfer operation (read is disabled when moden = 0 and write is disabled when moden = 1).
chapter 10 serial interface function user?s manual u12768ej4v1ud 223 10.2.2 csin control registers csin uses the following registers for control functions. serial clock select register n (csisn) serial operation mode register n (csimn) (1) serial clock select regi sters 0 to 2 (csis0 to csis2), serial ope ration mode registers 0 to 2 (csim0 to csim2) the csisn register is used to set of the serial clock serial interface channel n. the csisn register can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets csisn register the to 00h. the csimn register is used to enable or disable serial interface channel n?s serial clock, operation modes, and specific operations. the csimn register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the csimn register to 00h.
chapter 10 serial interface function user?s manual u12768ej4v1ud 224 after reset: 00h r/w address: csis0 fffff2a4h csis1 fffff2b4h csis2 fffff2c4h 7 6 5 4 3 2 1 0 csisn 0 0 0 0 0 0 0 scln2 after reset: 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim2 fffff2c2h 7 6 5 4 3 2 1 0 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0 to 2) sion operation enable/ disable specification shift register operation serial counter port 0 operation disable clear port function note 1 1 operation enable count operation enable serial function + port function note transfer operation mode flag operation mode transfer st art trigger son output 0 transmit/receive mode sion write normal output 1 receive-only mode sion read port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 at n = 0: tm2 output at n = 1, 2: tm3 output 0 1 0 fxx/8 (2.5 mhz) 0 1 1 fxx/16 (1.25 mhz) 1 0 0 setting prohibited 1 0 1 setting prohibited 1 1 0 fxx/32 (625 khz) 1 1 1 fxx/64 (312.5 khz) notes 1. when csien = 0 (sion operation stop status), t he sin, son, and sckn pi ns can be used as port functions. 2. when csien = 1 (sion operation enable status), t he sin pin when only using the transmit function and the son pin in receive-only m ode can be used as port functions. cautions 1. do not perform bit manipulation of scln1 and scln0. 2. be sure to set bits 3 to 6 of the csimn register to 0. remarks 1. values in parentheses apply when f xx = 20 mhz. 2. the selected clock is output fr om the timer, it is not nece ssary to set the p26/ti2/to2 and p27/t31/to3 pins to timer output mode. csien moden
chapter 10 serial interface function user?s manual u12768ej4v1ud 225 10.2.3 operations csin has the following two operation modes. operation stop mode 3-wire serial i/o mode (1) operation stop mode serial transfers are not performed in this m ode, enabling a reduction in power consumption. in operation stop mode, if t he sin, son, and sckn pins are also us ed as i/o ports, they can be used as normal i/o ports as well. (a) register settings operation stop mode is set via the csien bit of serial operation mode register n (csimn). figure 10-2. settings of csimn (operation stop mode) after reset : 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim2 fffff2c2h 7 6 5 4 3 2 1 0 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0 to 2) sion operation enable/ disable specification shift register operation serial counter port 0 operation disable clear port function csien
chapter 10 serial interface function user?s manual u12768ej4v1ud 226 (2) 3-wire serial i/o mode 3-wire serial i/o mode is useful when connecting to a peripher al i/o device that includes a clocked serial interface, a display controller, etc. this mode executes data transfers via three lines: a seri al clock line (sckn), serial output line (son), and serial input line (sin). (a) register settings 3-wire serial i/o mode is set via serial operation mode register n (csimn). figure 10-3. settings of cs imn (3-wire serial i/o mode) after reset : 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim2 fffff2c2h 7 6 5 4 3 2 1 0 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0 to 2) sion operation enable/ disable specification shift register operation serial counter port 1 operation enable count operation enabl e serial function + port function transfer operation mode flag operation mode transfer st art trigger son output 0 transmit/receive mode sion write normal output 1 receive-only mode sion read port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 when n = 0: tm2 output when n = 1, 2: tm3 output 0 1 0 fxx/8 (2.5 mhz) 0 1 1 fxx/16 (1.25 mhz) 1 0 0 setting prohibited 1 0 1 setting prohibited 1 1 0 fxx/32 (625 khz) 1 1 1 fxx/64 (312.5 khz) remarks 1. values in parentheses apply when f xx = 20 mhz. 2. refer to 10.2.2 (1) serial clo ck select registers 0 to 2 (csis0 to csis2), serial operation mode registers 0 to 2 (csim0 to csim2) for the scln2 bit. csien moden
chapter 10 serial interface function user?s manual u12768ej4v1ud 227 (b) communication operations in 3-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is transmitted or received in synchronization with the serial clock. serial i/o shift register n (sion) is shifted in synch ronization with the falling edge of the serial clock. transmission data is held in the son latc h and is output from the son pin. data that is received via the sin pin in synchronization with the rising edge of the serial clock is latched to sion. completion of an 8-bit transfer autom atically stops operation of sion and sets the interrupt request flag (intcsin). figure 10-4. timing of 3-wire serial i/o mode si0 di7 di6 di5 di4 di3 di2 di1 di0 intcsin serial clock 1 so0 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronization with the serial clock?s falling edge (c) transfer start a serial transfer starts when the following two c onditions have been satisfied and transfer data has been set to serial i/o shift register n (sion). the sion operation control bit (csien) = 1 after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. the transfer data is set to sion as follows. transmit/receive mode when csien = 1 and moden = 0, transfer starts when writing to sion. receive-only mode when csien = 1 and moden = 1, transfer starts when reading from sion. caution after data has been wri tten to sion, transfer will not start even if the csien bit value is set to ?1?. completion of an 8-bit transfer automat ically stops the serial transfer oper ation and sets the interrupt request flag (intcsin).
chapter 10 serial interface function user?s manual u12768ej4v1ud 228 10.3 i 2 c bus interface (i 2 c) to use the i 2 c bus function, set the p10/sda and p12/ scl pins to n-ch open-drain output. the products that incorporate i 2 c are shown below. pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, 70f3017ay i 2 c has the following two modes. operation stop mode i 2 c (inter ic) bus mode (mu lti-masters supported) (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. (2) i 2 c bus mode (multi -masters supported) this mode is used for 8-bit data transfers with several devic es via two lines: a serial clock (scl) line and a serial data bus (sda) line. this mode complies with the i 2 c bus format and the master device can out put ?start condition?, ?data?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects these received data by hardware. this f unction can simplify the part of an applic ation program that controls the i 2 c bus. since scl and sda are open- drain outputs, the i 2 c requires pull-up resistors for the serial clock line and the serial data bus line.
chapter 10 serial interface function user?s manual u12768ej4v1ud 229 figure 10-5. block diagram of i 2 c internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator match signal i ic shift register 0 (iic0) so latch iice d q set clear cl1, cl0 sda scl n-ch open drain output n-ch open drain output data hold time correction circuit ack detector wake up controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic0 f xx tm2 output cld iic clock select register 0 (iiccl0) iic function expansion register 0 (iicx0) internal bus lrel wrel spie wtim acke stt spt msts ald exc coi trc ackd std spd start condition detector dad smc dfc cl1 cl0 clx
chapter 10 serial interface function user?s manual u12768ej4v1ud 230 the following shows a serial bus configuration example. figure 10-6. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 10 serial interface function user?s manual u12768ej4v1ud 231 10.3.1 configuration i 2 c consists of the following hardware. table 10-2. configuration of i 2 c item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic clock select register 0 (iiccl0) iic function expansion register 0 (iicx0) (1) iic shift register 0 (iic0) iic0 is used to convert 8-bit serial data into 8-bit parallel data and vice versa. iic0 can be used for both transmission and reception. write and read operations to iic0 are used to contro l the actual transmit and receive operations. iic0 is set by an 8-bit memory manipulation instruction. reset input sets iic0 to 00h. (2) slave address register 0 (sva0) sva0 sets local addresses when in slave mode. sva0 is set by an 8-bit memory manipulation instruction. reset input sets sva0 to 00h. (3) so latch the so latch is used to retain the sda pin?s output level. (4) wakeup controller this circuit generates an interrupt request when the address received by this register matches the address value set to slave address register 0 (sva0) or when an extension code is received. (5) clock selector this selects the sampling clock to be used.
chapter 10 serial interface function user?s manual u12768ej4v1ud 232 (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signal (intiic0). an i 2 c interrupt is generated followi ng either of two triggers. ? eighth or ninth clock of the serial clock (set by wtim bit note ) ? interrupt request generated when a stop c ondition is detected (set by spie bit note ) note wtim bit: bit 3 of iic control register 0 (iicc0) spie bit: bit 4 of iic control register 0 (iicc0) (8) serial clock controller in master mode, this circuit generates the clo ck output via the scl pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector , start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock.
chapter 10 serial interface function user?s manual u12768ej4v1ud 233 10.3.2 i 2 c control registers i 2 c is controlled by four types of registers. iic control register 0 (iicc0) iic status register 0 (iics0) iic function expansion register 0 (iicx0) iic clock select register 0 (iiccl0) the following registers are also used. iic shift register 0 (iic0) slave address register 0 (sva0)
chapter 10 serial interface function user?s manual u12768ej4v1ud 234 (1) iic control register 0 (iicc0) iicc0 is used to enable/disable i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 can be set by a 1-bit or 8-bi t memory manipulation instruction. reset input sets iicc0 to 00h. caution in i 2 c bus mode, set the port 1 mode register (pm1) as follows. in addition, set each output latch to 0. ? set p10 (sda) to output mode (pm10 = 0) ? set p12 (scl) to output mode (pm12 = 0) (1/4) after reset: 00h r/w address: fffff340h 7 6 5 4 3 2 1 0 iicc0 iice lrel wrel spie wtim acke stt spt iice i 2 c operation enable/di sable specification 0 operation stopped. iic status register 0 (iics0) preset. internal operation stopped. 1 operation enabled. condition for clearing (iice = 0) condition for setting (iice = 1) ? cleared by instruction ? when reset is input ? set by instruction lrel exit from communications 0 normal operation 1 this exits from the current communications operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelev ant extension code has been received. the scl and sda lines are set to high impedance. the following flags are cleared. ? std ? ackd ? trc ? coi ? exc ? msts ? stt ? spt the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rec eption occurs after the start condition. condition for clearing (lrel = 0) note condition for setting (lrel = 1) ? automatically cleared after execution ? when reset is input ? set by instruction note this flag?s signal is invalid when iice = 0. remark std: bit 1 of iic status register 0 (iics0) ackd: bit 2 of iic status register 0 (iics0) trc: bit 3 of iic status register 0 (iics0) coi: bit 4 of iic status register 0 (iics0) exc: bit 5 of iic status register 0 (iics0) msts: bit 7 of iic status register 0 (iics0)
chapter 10 serial interface function user?s manual u12768ej4v1ud 235 (2/4) wrel wait cancellation control 0 wait not canceled 1 wait canceled. this setting is automat ically cleared after wait is canceled. condition for clearing (wrel = 0) note condition for setting (wrel = 1) ? automatically cleared after execution ? when reset is input ? set by instruction spie enable/disable generation of interr upt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spie = 0) note condition for setting (spie = 1) ? cleared by instruction ? when reset is input ? set by instruction wtim control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for the master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for the master device. this bit?s setting is invalid during an addr ess transfer and is valid as the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock duri ng address transfers. for a slav e device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim = 0) note condition for setting (wtim = 1) ? cleared by instruction ? when reset is input ? set by instruction acke acknowledge control 0 acknowledgement disabled. 1 acknowledge enabled. during the ninth clock period, the sda line is set to low level. however, the ack is invalid during address transfe rs and is valid when exc = 1. condition for clearing (acke = 0) note condition for setting (acke = 1) ? cleared by instruction ? when reset is input ? set by instruction note this flag?s signal is invalid when iice = 0.
chapter 10 serial interface function user?s manual u12768ej4v1ud 236 (3/4) stt start condition trigger 0 start conditions not generated. 1 when bus is released (in stop mode): generate a start condition (for starting as maste r). the sda line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scl is changed to low level. when bus is not used: this trigger functions as a st art condition reserve flag. when set, it releases the bus and then automatically generates a start condition. in the wait state (when master device): generate a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set during transfe r. can be set only when acke has been set to 0 and slave has been notified of final reception. ? for master transmission: note that a start c ondition cannot be generated normally during the ack period. ? cannot be set at the same time as sptn condition for clearing (stt = 0) condition for setting (stt = 1) ? cleared by instruction ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? cleared by lrel = 1 ? when iice = 0 ? cleared when reset is input ? set by instruction remark bit 1 (stt) is 0 if it is read immediately after data setting.
chapter 10 serial interface function user?s manual u12768ej4v1ud 237 (4/4) spt stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda line goes to low level, either set t he scl line to high level or wait until it goes to high level. next, after the rated amount of ti me has elapsed, the sda line is changed from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only during the wait period when acke has been set to 0 and slave has been notified of final reception. ? for master transmission: note that a stop condi tion cannot be generated normally during the ack period. set a stop condition during the wait period. ? cannot be set at the same time as stt. ? spt can be set only when in master mode. note ? when wtim has been set to 0, if spt is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. when a ninth clock must be output, wtim should be c hanged from 0 to 1 during the wait period following output of eight clocks, and spt should be set during the wait period that follows output of the ninth clock. condition for clearing (spt = 0) condition for setting (spt = 1) ? cleared by instruction ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? cleared by lrel = 1 ? when iice = 0 ? cleared when reset is input ? set by instruction note set spt only in master mode. however, spt must be set and a stop c ondition generated before the first stop condition is detected following the swit ch to operation enable status. for details, see 10.3.13 cautions . caution when bit 3 (trc) of iic status register 0 (iics0) is set to 1, wrel is set during the ninth clock and wait is canceled, after which trc is cleared and the sda line is set to high impedance. remark bit 0 (spt) is 0 if it is r ead immediately after data setting.
chapter 10 serial interface function user?s manual u12768ej4v1ud 238 (2) iic status register 0 (iics0) iics0 indicates the status of the i 2 c bus. iics0 can be set by a 1-bit or 8-bit memory manipul ation instruction. iics0 is a read-only register. reset input sets iics0 to 00h. (1/3) after reset: 00h r address: fffff342h 7 6 5 4 3 2 1 0 iics0 msts ald exc coi trc ackd std spd msts master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts = 0) condition for setting (msts = 1) ? when a stop condition is detected ? when ald = 1 ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? when reset is input ? when a start condition is generated ald detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. msts is cleared. condition for clearing (ald = 0) condition for setting (ald = 1) ? automatically cleared after iics is read note ? when iice changes from 1 to 0 ? when reset is input ? when the arbitration result is a ?loss?. note this register is also cleared when a bit manipulati on instruction is executed for bits other than iics0. remark lrel: bit 6 of iic control register 0 (iicc0) iice: bit 7 of iic control register 0 (iicc0)
chapter 10 serial interface function user?s manual u12768ej4v1ud 239 (2/3) exc detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc = 0) condition for setting (exc = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? when reset is input ? when the higher four bits of the received address data are either ?0000? or ?1111? (set at the rising edge of the eighth clock). coi detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi = 0) condition for setting (coi = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? when reset is input ? when the received address matches the local address (sva0) (set at the rising edge of the eighth clock). trc detection of transmit/receive status 0 receive status (other than transmit status ). the sda line is set to high impedance. 1 transmit status. the value in the so latch is enabled for output to t he sda line (valid starting at the rising edge of the first byte?s ninth clock). condition for clearing (trc = 0) condition for setting (trc = 1) ? when a stop condition is detected ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? cleared by wrel = 1 note ? when ald changes from 0 to 1 ? when reset is input master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) note when bit 3 (trc) of iic status register 0 (iics0) is 1, if a wait is released by setting bit 5 (wrel) of iic control register 0 (iicc0) at the 9th clock, the sda line becomes high impedance after trc is cleared. remark lrel: bit 6 of iic control register 0 (iicc0) iice: bit 7 of iic control register 0 (iicc0)
chapter 10 serial interface function user?s manual u12768ej4v1ud 240 (3/3) ackd detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackd = 0) condition for setting (ackd = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? when reset is input ? after the sda line is set to low level at the rising edge of the scl?s ninth clock std detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std = 0) condition for setting (std = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? when reset is input ? when a start condition is detected spd detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master devic e?s communication is terminated and the bus is released. condition for clearing (spd = 0) condition for setting (spd = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when iice changes from 1 to 0 ? when reset is input ? when a stop condition is detected remark lrel: bit 6 of iic control register 0 (iicc0) iice: bit 7 of iic control register 0 (iicc0)
chapter 10 serial interface function user?s manual u12768ej4v1ud 241 (3) iic clock select register 0 (iiccl0) , iic function expansion register 0 (iicx0) the iiccl0 and iicx0 registers are used to set the transfer clock for the i 2 c bus. the iiccl0 and iicx0 registers can be set by an 8-bi t or 1-bit memory manipulation instruction. reset input sets these registers to 00h. (1/2) after reset: 00h r/w address: fffff34ah 7 6 5 4 3 2 1 0 iicx0 0 0 0 0 0 0 0 clx after reset: 00h r/w note address: fffff344h 7 6 5 4 3 2 1 0 iiccl0 0 0 cld dad smc dfc cl1 cl0 cld detection of scl line level (valid only when iice = 1) 0 scl line was detected at low level. 1 scl line was detected at high level. condition for clearing (cld = 0) condition for setting (cld = 1) ? when the scl line is at low level ? when iice = 0 ? when reset is input ? when the scl line is at high level dad detection of sda line level (valid only when iice = 1) 0 sda line was detected at low level. 1 sda line was detected at high level. condition for clearing (dad = 0) condition for setting (dad = 1) ? when the sda line is at low level ? when iice = 0 ? when reset is input ? when the sda line is at high level smc operation mode switching 0 operated in standard mode 1 operated in high-speed mode dfc operation control of digital filter 0 digital filter off 1 digital filter on a digital filter can be used only in high-speed mode. the transfer clock does not change by se tting dfc on/off in the high-speed mode. note bits 4 and 5 of the iiccl0 register are read-only bits. caution be sure to set bits 6 a nd 7 of the iiccl0 register to 0. remark iice: bit 7 of iic control register 0 (iicc0)
chapter 10 serial interface function user?s manual u12768ej4v1ud 242 (2/2) clx smc cl1 cl0 selection clock range of settable main clock frequency (f xx ) operation mode 0 0 0 0 f xx /44 2.0 mhz to 4.19 mhz 0 0 0 1 f xx /86 4.19 mhz to 8.38 mhz 0 0 1 0 f xx /172 8.38 mhz to 17 mhz 0 0 1 1 tm2 output/66 tm2 setting standard mode (smc = 0) 0 1 0 0 0 1 0 1 f xx /24 4.0 mhz to 8.38 mhz 0 1 1 0 f xx /48 8.0 mhz to 17 mhz 0 1 1 1 tm2 output/18 tm2 setting 1 1 0 0 1 1 0 1 f xx /12 4.0 mhz to 4.19 mhz high-speed mode (smc = 1) other than above setting prohibited remark when the selected clock is the timer output, it is not necessary to set the p26/ti2/to2 pin to timer output mode. (5) iic shift register 0 (iic0) iic0 is used for serial transmission/reception (shift operations ) that are synchronized with the serial clock. it can be read from or written to in 8-bit units, but data should not be written to iic0 during a data transfer. after reset: 00h r/w address: fffff348h 7 6 5 4 3 2 1 0 iic0 (6) slave address register 0 (sva0) sva0 holds the i 2 c bus?s slave addresses. it can be read from or written to in 8-bit units, but bit 0 should be fixed to 0. after reset: 00h r/w address: fffff346h 7 6 5 4 3 2 1 0 sva0 0
chapter 10 serial interface function user?s manual u12768ej4v1ud 243 10.3.3 i 2 c bus mode functions (1) pin configuration the serial clock pin (scl) and serial data bus pin (sda) are configured as follows. scl ................ this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda ................ this pi n is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial dat a bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 10-7. pin configuration diagram v dd scl sda scl sda v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 10 serial interface function user?s manual u12768ej4v1ud 244 10.3.4 i 2 c bus definitions a nd control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. figure 10-8 shows the transfer timing for the ?start c ondition?, ?data?, and ?stop c ondition? output via the i 2 c bus?s serial data bus. figure 10-8. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl sda start condition address r/w ack data data stop condition ack ack the master device outputs t he start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave dev ice (normally, it is output by the device that receives 8-bit data). the serial clock (scl) is continuously output by the master devic e. however, in the sl ave device, the scl?s low- level period can be extended and a wait can be inserted. (1) start condition the start condition is met when the scl pin is at high leve l and the sda pin changes from high level to low level. the start conditions for the scl pin and sda pin are signal s that the master device outputs to the slave device when starting a serial transfer. the slave devic e includes hardware for detecting start conditions. figure 10-9 start condition h scl sda a start condition is output when bit 1 (stt) of iic control register 0 (iicc0) is set to 1 after a stop condition has been detected (spd: bit 0 = 1 in iic status register 0 (iic s0)). when a start condition is detected, bit 1 (std) of iics0 is set to 1.
chapter 10 serial interface function user?s manual u12768ej4v1ud 245 (2) addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via bus lines. t herefore, each slave devic e connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in slave address register 0 (sva0). if the address data matches the sva0 values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. figure 10-10. address address scl 1 sda intiic0 note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note intiic0 is generated if a local address or extens ion code is received duri ng slave device operation. the slave address and the eighth bit, which specif ies the transfer direction as described in (3) transfer direction specification below, are written together to iic shift regist er 0 (iic0) and are then output. received addresses are written to iic0. the slave address is assigned to the higher 7 bits of iic0.
chapter 10 serial interface function user?s manual u12768ej4v1ud 246 (3) transfer direction specification in addition to the 7-bit address data, the master device transmits 1-bit data that specifies the transfer direction. when this transfer direction specificati on bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicate s that the master device is receiving data from a slave device. figure 10-11. transfer direction specification scl 1 sda intiic0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note intiic0 is generated if a local address or extens ion code is received duri ng slave device operation.
chapter 10 serial interface function user?s manual u12768ej4v1ud 247 (4) acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and re ceiving devices to confirm serial data reception. the receiving device returns one ack signal for every 8 bits of data it receives. t he transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master devic e is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. t he transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the curr ent transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sda line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acke) of iic control register 0 (iicc0) is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following t he 7 address data bits causes bit 3 (trc) of iic status register 0 (iics0) to be set. when this trc bit?s value is 0, it indica tes receive mode. therefore, acke should be set to 1. when the slave device is receiving (w hen trc = 0), if the slave device does not need to receive any more data after receiving several bytes, setting acke to 0 will prev ent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trc = 0) and the subs equent data is not needed and when either a restart condition or a stop condition should t herefore be output, setting acke to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda line (i.e., stops transmission) during transmissi on from the slave device. figure 10-12. ack signal scl 1 sda 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack
chapter 10 serial interface function user?s manual u12768ej4v1ud 248 when the local address is received, an ack signal is aut omatically output in synch ronization with the falling edge of the scl?s eighth clock regardless of the acke value. no ack signal is output if the received address is not a local address. the ack signal output method during dat a reception is based on the wait timing setting, as described below. when 8-clock wait is selected: ack signal is output at the falling edge of the scl?s eighth clock when acke is set to 1 before wait cancellation. when 9-clock wait is selected: ack signal is automatically out put at the falling edge of t he scl?s eighth clock if acke has already been set to 1. (5) stop condition when the scl pin is at high level, changing the sda pin from low level to high level generates a stop condition. a stop condition is a signal that t he master device outputs to the slav e device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 10-13. stop condition h scl sda a stop condition is generated when bit 0 ( spt) of iic control register 0 (ii cc0) is set to 1. when the stop condition is detected, bit 0 (spd0) of iic status register 0 (iics0) is se t to 1 and intiic0 is generated when bit 4 (spie0) of iicc0 is set to 1.
chapter 10 serial interface function user?s manual u12768ej4v1ud 249 (6) wait signal (wait) the wait signal (wait) is used to notif y the communication partner that a devic e (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl pin to low level notifies the communication par tner of the wait status. when the wait status has been canceled for both the master and slave devices, the next data transfer can begin. figure 10-14. wait signal (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, sl ave: reception, and acke = 1) scl 6 sda 78 9 123 scl iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl acke master master returns to high impedance but slave is in wait state (low level) wait after output of ninth clock iic0 data write (cancel wait) slave wait after output of eighth clock ffh is written to iic0 or wrel is set to 1 transfer lines
chapter 10 serial interface function user?s manual u12768ej4v1ud 250 figure 10-14. wait signal (2/2) (b) when master and slave d evices both have a nine-clock wait (master: transmission, sl ave: reception, and acke = 1) scl 6 sda 789 123 scl iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl acke master master and slave both wait after output of ninth clock iic0 data write (cancel wait) slave ffh is written to iic0 or wrel is set to 1 output according to previously set acke value transfer lines remark acke: bit 2 of iic control register 0 (iicc0) wrel: bit 5 of iic control register 0 (iicc0) a wait may be automatically generated dependi ng on the setting for bit 3 (wtim) of iic control register 0 (iicc0). normally, when bit 5 (wrel) of iicc0 is set to 1 or when ffh is written to iic shift register 0 (iic0), the wait status is canceled and the transmitting side writes dat a to iic0 to cancel the wait status. the master device can also c ancel the wait status via ei ther of the following methods. by setting bit 1 (stt) of iicc0 to 1 by setting bit 0 (spt) of iicc0 to 1
chapter 10 serial interface function user?s manual u12768ej4v1ud 251 10.3.5 i 2 c interrupt request (intiic0) the following shows the value of iic st atus register 0 (iics0) at the int iic0 interrupt request generation timing and at the intiic0 interrupt timing. remark the interrupt control regist er of intiic0 is alternately used as t he interrupt control register (csic0) of intcsi0. an iicic0 register does not exist. (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtim = 0 spt = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 10xxx110b 2: iics0 = 10xxx000b 3: iics0 = 10xxx000b (wtim = 1) 4: iics0 = 10xxxx00b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 spt = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 10xxx110b 2: iics0 = 10xxx100b 3: iics0 = 10xxxx00b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 252 (b) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtim = 0 stt = 1 spt = 1 st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 ? 7 1: iics0 = 10xxx110b 2: iics0 = 10xxx000b (wtim = 1) 3: iics0 = 10xxxx00b (wtim = 0) 4: iics0 = 10xxx110b 5: iics0 = 10xxx000b (wtim = 1) 6: iics0 = 10xxxx00b ? 7: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 stt = 1 spt = 1 st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 10xxx110b 2: iics0 = 10xxxx00b 3: iics0 = 10xxx110b 4: iics0 = 10xxxx00b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 253 (c) start ~ code ~ da ta ~ data ~ stop (extension code transmission) <1> when wtim = 0 spt = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 1010x110b 2: iics0 = 1010x000b 3: iics0 = 1010x000b (wtim = 1) 4: iics0 = 1010xx00b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 spt = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 1010x110b 2: iics0 = 1010x100b 3: iics0 = 1010xx00b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 254 (2) slave device operation (when recei ving slave address data (matches sva0)) (a) start ~ address ~ data ~ data ~ stop <1> when wtim = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0001x110b 2: iics0 = 0001x000b 3: iics0 = 0001x000b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0001x110b 2: iics0 = 0001x100b 3: iics0 = 0001xx00b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 255 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, matches sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0001x110b 2: iics0 = 0001x000b 3: iics0 = 0001x110b 4: iics0 = 0001x000b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, matches sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0001x110b 2: iics0 = 0001xx00b 3: iics0 = 0001x110b 4: iics0 = 0001xx00b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 256 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim = 0 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0001x110b 2: iics0 = 0001x000b 3: iics0 = 0010x010b 4: iics0 = 0010x000b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 ? 6 1: iics0 = 0001x110b 2: iics0 = 0001xx00b 3: iics0 = 0010x010b 4: iics0 = 0010x110b 5: iics0 = 0010xx00b ? 6: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 257 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, do es not match address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0001x110b 2: iics0 = 0001x000b 3: iics0 = 00000x10b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, do es not match address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0001x110b 2: iics0 = 0001xx00b 3: iics0 = 00000x10b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 258 (3) slave device operation (w hen receiving extension code) (a) start ~ code ~ data ~ data ~ stop <1> when wtim = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0010x010b 2: iics0 = 0010x000b 3: iics0 = 0010x000b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0010x010b 2: iics0 = 0010x110b 3: iics0 = 0010x100b 4: iics0 = 0010xx00b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 259 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, matches sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0010x010b 2: iics0 = 0010x000b 3: iics0 = 0001x110b 4: iics0 = 0001x000b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, matches sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 ? 6 1: iics0 = 0010x010b 2: iics0 = 0010x110b 3: iics0 = 0010xx00b 4: iics0 = 0001x110b 5: iics0 = 0001xx00b ? 6: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 260 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop <1> when wtim = 0 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0010x010b 2: iics0 = 0010x000b 3: iics0 = 0010x010b 4: iics0 = 0010x000b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 ? 7 1: iics0 = 0010x010b 2: iics0 = 0010x110b 3: iics0 = 0010xx00b 4: iics0 = 0010x010b 5: iics0 = 0010x110b 6: iics0 = 0010xx00b ? 7: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 261 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, do es not match address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0010x010b 2: iics0 = 0010x000b 3: iics0 = 00000x10b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, do es not match address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0010x010b 2: iics0 = 0010x110b 3: iics0 = 0010xx00b 4: iics0 = 00000x10b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 262 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp ? 1 ? 1: iics0 = 00000001b remark ? : generated only when spie = 1 (5) arbitration loss operation (opera tion as slave after arbitration loss) (a) when arbitration loss occurs dur ing transmission of slave address data <1> when wtim = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0101x110b (example: when ald is read during interrupt servicing) 2: iics0 = 0001x000b 3: iics0 = 0001x000b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0101x110b (example: when ald is read during interrupt servicing) 2: iics0 = 0001x100b 3: iics0 = 0001xx00b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 263 (b) when arbitration loss occurs dur ing transmission of extension code <1> when wtim = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 0110x010b (example: when ald is read during interrupt servicing) 2: iics0 = 0010x000b 3: iics0 = 0010x000b ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 ? 5 1: iics0 = 0110x010b (example: when ald is read during interrupt servicing) 2: iics0 = 0010x110b 3: iics0 = 0010x100b 4: iics0 = 0010xx00b ? 5: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 264 (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs dur ing transmission of slave address data st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 ? 2 1: iics0 = 01000110b (example: when ald is read during interrupt servicing) ? 2: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 (b) when arbitration loss occurs during transmission of extension code st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 ? 2 1: iics0 = 0110x010b (example: when ald is read during interrupt servicing) iicc0: lrel is set to 1 by software ? 2: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 265 (c) when arbitration loss o ccurs during data transfer <1> when wtim = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 ? 3 1: iics0 = 10001110b 2: iics0 = 01000000b (example: when ald is read during interrupt servicing) ? 3: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 <2> when wtim = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 ? 3 1: iics0 = 10001110b 2: iics0 = 01000100b (example: when ald is read during interrupt servicing) ? 3: iics0 = 00000001b remark : always generated ? : generated only when spie = 1
chapter 10 serial interface function user?s manual u12768ej4v1ud 266 (d) when loss occurs due to rest art condition during data transfer <1> not extension code (example: does not match sva0) st ad6-ad0 rw ak d7-dn st ad6-ad0 rw ak d7-d0 ak sp 1 2 ? 3 1: iics0 = 1000x110b 2: iics0 = 01000110b (example: when ald is read during interrupt servicing) ? 3: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care dn = d6 to d0 <2> extension code st ad6-ad0 rw ak d7-dn st ad6-ad0 rw ak d7-d0 ak sp 1 2 ? 3 1: iics0 = 1000x110b 2: iics0 = 0110x010b (example: when ald is read during interrupt servicing) iicc0: lrel is set to 1 by software ? 3: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care dn = d6 to d0
chapter 10 serial interface function user?s manual u12768ej4v1ud 267 (e) when loss occurs due to st op condition during data transfer st ad6-ad0 rw ak d7-dn sp 1 ? 2 1: iics0 = 1000x110b ? 2: iics0 = 01000001b remark : always generated ? : generated only when spie = 1 x: don?t care dn = d6 to d0 (f) when arbitration loss occurs due to low-level da ta when attempting to gene rate a restart condition when wtim = 1 stt = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 1000x110b 2: iics0 = 1000xx00b 3: iics0 = 01000100b (example: when ald is read during interrupt servicing) ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 268 (g) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition when wtim = 1 stt = 1 st ad6-ad0 rw ak d7-d0 ak sp 1 2 ? 3 1: iics0 = 1000x110b 2: iics0 = 1000xx00b ? 3: iics0 = 01000001b remark : always generated ? : generated only when spie = 1 x: don?t care (h) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition when wtim = 1 spt = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 ? 4 1: iics0 = 1000x110b 2: iics0 = 1000xx00b 3: iics0 = 01000000b (example: when ald is read during interrupt servicing) ? 4: iics0 = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care
chapter 10 serial interface function user?s manual u12768ej4v1ud 269 10.3.6 interrupt request (intiic0) ge neration timing and wait control the setting of bit 3 (wtim) of iic control register 0 ( iicc0) determines the timing by which intiic0 is generated and the corresponding wait control, as shown below. table 10-3. intiicn genera tion timing and wait control during slave device operation du ring master device operation wtim address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic0 signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the address set to the slave address register (sva0). at this point, ack is output regardless of the value set to bit 2 (acke) of iicc0. for a slave device that has received an extension code, intiic0 occu rs at the falling edge of the eighth clock. 2. if the received address does not ma tch the contents of the slave addr ess register (sva0), neither intiic0 nor a wait occurs. remark the numbers in the table indicate the number of the serial clock si gnals. interrupt requests and wait control are both synchronized with t he falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait ti ming are determined regardless of the wtim bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting bit 5 (wrel) of iic control register 0 (iicc0) to 1 ? by writing to iic shift register 0 (iic0) ? by setting start condition (bit 1 (stt) of iic control register 0 (iicc0) = 1) ? by setting stop condition (bit 0 (spt) of iic control register 0 (iicc0) = 1) when an 8-clock wait has been selected (wtim = 0), the out put level of ack must be determined prior to wait cancellation. (5) stop condition detection intiic0 is generated when a st op condition is detected.
chapter 10 serial interface function user?s manual u12768ej4v1ud 270 10.3.7 address match detection method in i 2 c bus mode, the master dev ice can select a particular slave devic e by transmitting the corresponding slave address. address match detection is performed aut omatically by hardware. an inte rrupt request (intiic0) occurs when a local address has been set to slave address register 0 ( sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 10.3.8 error detection in i 2 c bus mode, the status of the serial data bus (sda) during data transmi ssion is captured by iic shift register 0 (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmissi on error is judged as having occurred when the compared data values do not match. 10.3.9 extension code (1) when the higher 4 bits of the receive address are ei ther 0000 or 1111, the extensi on code reception flag (exc) is set for extension code reception and an interrupt request (intiic0) is i ssued at the falling edge of the eighth clock. the local address stored in slave addre ss register 0 (sva0) is not affected. (2) if 11110xx0 is set to sva0 by a 10-bit address transfe r and 11110xx0 is transferred from the master device, the results are as follows. note that intiic0 occurs at the falling edge of the eighth clock. ? higher four bits of data match: exc = 1 note ? seven bits of data match: coi = 1 note note exc: bit 5 of iic status register 0 (iics0) coi: bit 4 of iic status register 0 (iics0) (3) since the processing after the interrupt request occurs differs according to the dat a that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set bit 6 of iic control register 0 (iicc0) to lrel = 1 and the cpu will enter the next communi cation wait state. table 10-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for a different bus format 1111 0xx x 10-bit slave address specification
chapter 10 serial interface function user?s manual u12768ej4v1ud 271 10.3.10 arbitration when several master devices simultaneous ly output a start condition (when stt is set to 1 before std is set to 1 note ), communication among the master devices is performed as the number of clo cks is adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in ar bitration, an arbitration loss flag (ald) in iic status register 0 (iics0) is set at the timing by which the arbitration loss occurr ed, and the scl and sda lines ar e both set to high impedance, which releases the bus. the arbitration loss is detec ted based on the timing of the next interrupt request (the eight h or ninth clock, when a stop condition is detected, et c.) and the ald = 1 setting that has been made by software. for details of interrupt request timing, see 10.3.5 i 2 c interrupt request (intiic0) . note std: bit 1 of iic status register 0 (iics0) stt: bit 1 of iic control register 0 (iicc0) figure 10-15. arbitration timing example master 1 master 2 transfer lines scl sda scl sda scl sda master 1 loses arbitration hi-z hi-z
chapter 10 serial interface function user?s manual u12768ej4v1ud 272 table 10-5. status during arbitration and interrupt request generation timing status during arbitration inte rrupt request generation timing during address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data reception when restart condition is det ected during data transfer when stop condition is detec ted during data transfer when stop condition is output (when spie = 1) note 2 when data is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spie = 1) note 2 when data is at low level while attempting to output a stop condition at falling edge of eighth or ninth clock following byte transfer note 1 when scl is at low level while attempting to output a restart condition notes 1. when wtim (bit 3 of iic control register 0 (iicc0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim = 0 and the extension code?s slave addr ess is received, an interrupt request occurs at the falli ng edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set spie = 1 for master device operation. remark spie: bit 5 of iic control register 0 (iicc0) 10.3.11 wakeup function the i 2 c bus slave function is a functi on that generates an inte rrupt request (intiic0) when a local address and extension code have been received. th is function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 5 (spie) of iic control register 0 (iicc0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled.
chapter 10 serial interface function user?s manual u12768ej4v1ud 273 10.3.12 communication reservation to start master device communications when not current ly using the bus, a communication reservation can be made to enable transmission of a start c ondition when the bus is released. t here are two modes under which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel) of iic control register 0 (iicc0) was set to 1). if bit 1 (stt) of iicc0 is set while the bus is not used, a start condition is automatica lly generated and a wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to iic shift register 0 (iic0) causes the master?s address transfer to start. at th is point bit 4 (spie) of iicc0 should be set. when stt has been set, the operation mode (as start conditi on or as communication reservation) is determined according to the bus status. if the bus has been re leased.................................................. a start condition is generated if the bus has not been released (standby mode) .................. comm unication reservation to detect which operation mode has been det ermined for stt, set stt, wait for the wait period, then check msts (bit 7 of iic status register 0 (iics0)). wait periods, which should be set via software, are listed in table 10-6. these wait periods can be set via the settings for bits 3, 1, and 0 (smc, cl1, and cl0) of iic clock select register 0 (iiccl0). table 10-6. wait periods smc cl1 cl0 wait period 0 0 0 26 clocks 0 0 1 46 clocks 0 1 0 92 clocks 0 1 1 37 clocks 1 0 0 16 clocks 1 0 1 1 1 0 32 clocks 1 1 1 13 clocks
chapter 10 serial interface function user?s manual u12768ej4v1ud 274 the communication reservation timing is shown below. figure 10-16. communication reservation timing iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are acknowl edged at the following timing. after bit 1 (std) of iic status register 0 (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt) of iic control register 0 (iicc0) to 1 before a stop condi tion is detected. figure 10-17. timing for ackno wledging communication reservations 2 1 3456 2 1 3456 789 scl sda program processing hardware processing write to iic0 set spd and intiic0 stt =1 communication reservation set std output by master with bus mastership scl sda std spd standby mode
chapter 10 serial interface function user?s manual u12768ej4v1ud 275 the communication reservation flow chart is illustrated below. figure 10-18. communication reservation flow chart note the communication reservation operat ion executes a write to iic shi ft register 0 (iic0) when a stop condition interrupt request occurs. di set1 stt define communication reservation wait cancel communication reservation no yes iic0 xxh ei msts = 0? (communication reservation) note (generate start condition) ; sets stt flag (communication reservation). ; gets wait period set by software (see table 10-6 ). ; confirmation of communication reservation ; clear user flag. ; iic0 write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram).
chapter 10 serial interface function user?s manual u12768ej4v1ud 276 10.3.13 cautions after a reset, when changing from a mode in which no stop condition has been detec ted (the bus has not been released) to a master device communication mode, firs t generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master devic e communication when the bus has not been released (when a stop condi tion has not been detected). use the following sequence for generating a stop condition. (a) set iic clock select register 0 (iiccl0). (b) set bit 7 (iice) of iic control register 0 (iicc0). (c) set bit 0 of iicc0.
chapter 10 serial interface function user?s manual u12768ej4v1ud 277 10.3.14 communication operations (1) master operations the following is a flow char t of the master operations. figure 10-19. master operation flow chart iiccl0 xxh select transfer clock. iicc0 xxh iice = spie = wtim = 1 stt = 1 start iic0 write transfer. start iic0 write transfer. wrel = 1 start reception. generate stop condition. (no slave with matching address) generate restart condition or stop condition. start data processing data processing acke = 0 no yes no no no no no no yes yes yes yes yes yes intiic0 = 1? wtim = 0 acke = 1 intiic0 = 1? transfer completed? intiic0 = 1? ackd = 1? trc = 1? intiic0 = 1? ackd = 1? ; stop condition detection ; address transfer completion no (receive) yes (transmit)
chapter 10 serial interface function user?s manual u12768ej4v1ud 278 (2) slave operation the following is a flow chart of the slave operations. figure 10-20. slave operation flow chart iicc0 h iice = 1 wrel = 1 start reception. acke = 0 wrel = 1 detect restart condition or stop condition. start data processing data processing lrel = 1 no yes no no no (receive) no no no no yes no yes yes yes (transmit) yes yes yes wtim = 0 acke = 1 intiic0 = 1? yes communicate? transfer completed? intiic0 = 1? wtim = 1 start iic0 write transfer. wrel = 1 wait release intiic0 = 1? exc = 1? coi = 1? trc = 1? ackd = 1?
chapter 10 serial interface function user?s manual u12768ej4v1ud 279 10.3.15 timing of data communication when using i 2 c bus mode, the master device out puts an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the mast er device transmits the trc bit (bit 3 of iic status register 0 (iics0)) that specifies the data transfer di rection and then starts serial co mmunication with the slave device. the shift operation of iic bus shift register 0 (iic0) is synchronized with the falling edge of the serial clock (scl). the transmit data is transferred to the so latc h and is output (msb first) via the sda pin. data input via the sda pin is captur ed by iic0 at the rising edge of scl. the following shows the timing c harts of data communication.
chapter 10 serial interface function user?s manual u12768ej4v1ud 280 figure 10-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address note to cancel slave wait, writ e ffh to iic0 or set wrel. iic0 ackd std spd wtim h h l l l l h h h l l acke msts stt spt wrel intiic0 trc iic0 ackd std spd wtim acke msts stt spt wrel intiic0 trc scl sda processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc = 1) note note
chapter 10 serial interface function user?s manual u12768ej4v1ud 281 figure 10-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data note to cancel slave wait, writ e ffh to iic0 or set wrel. iic0 ackd std spd wtim h h l l l l l l h h h h l l l l l acke msts stt spt wrel intiic0 trc iic0 ackd std spd wtim acke msts stt spt wrel intiic0 trc scl sda processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh note iic0 ffh note iic0 data transmit receive note note
chapter 10 serial interface function user?s manual u12768ej4v1ud 282 figure 10-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition note to cancel slave wait, writ e ffh to iic0 or set wrel. iic0 ackd std spd wtim h h l l l l h h h l acke msts stt spt wrel intiic0 trc iic0 ackd std spd wtim acke msts stt spt wrel intiic0 trc scl sda processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie = 1) receive (when spie = 1)
chapter 10 serial interface function user?s manual u12768ej4v1ud 283 figure 10-22. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address note to cancel master wait, wr ite ffh to iic0 or set wrel. iic0 ackd std spd wtim h h l l h h l acke msts stt l l spt wrel intiic0 trc iic0 ackd std spd wtim acke msts stt spt wrel intiic0 trc scl sda processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition
chapter 10 serial interface function user?s manual u12768ej4v1ud 284 figure 10-22. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data note to cancel master wait, wr ite ffh to iic0 or set wrel. iic0 ackd std spd wtim h h h l l l l l l h h h l l l l l acke msts stt spt wrel intiic0 trc iic0 ackd std spd wtim acke msts stt spt wrel intiic0 trc scl sda processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note
chapter 10 serial interface function user?s manual u12768ej4v1ud 285 figure 10-22. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition note to cancel master wait, wr ite ffh to iic0 or set wrel. iic0 ackd std spd wtim h h l l l h h acke msts stt spt wrel intiic0 trc iic0 ackd std spd wtim acke msts stt spt wrel intiic0 trc scl sda processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie = 1) n ? ack (when spie = 1)
chapter 10 serial interface function user?s manual u12768ej4v1ud 286 10.4 asynchronous serial interface (uart0, uart1) uartn (n = 0, 1) has the following two operation modes. (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. (2) asynchronous serial interface (uart) mode this mode enables full-duplex operation in which one byte of data is transmitted and received after the start bit. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. in addition, a baud rate based on divided cl ock input to the asckn pin can also be defined. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). 10.4.1 configuration uartn consists of t he following hardware. table 10-7. configuration of uartn item configuration registers transmit shift r egisters 0, 1 (txs0, txs1) receive buffer registers 0, 1 (rxb0, rxb1) control registers asynchronous serial in terface mode registers 0, 1 (asim0, asim1) asynchronous serial interface stat us registers 0, 1 (asis0, asis1) baud rate generator control registers 0, 1 (brgc0, brgc1) baud rate generator mode control registers 0, 1 (brgmc0, brgmc1) baud rate generator mode control register 01 (brgmc01)
chapter 10 serial interface function user?s manual u12768ej4v1ud 287 figure 10-23. block diagram of uartn baud ? rate ? generator f xx ? to ? f xx /2 9 txd0, ? txd1 asck0, ? asck1 rxd0, ? rxd1 intst0, intst1 intsr0, intsr1 0, ? 1 ? (rx0, ? rx1) internal ? bus selector 0, ? 1 ? (txs0, ? txs1) 8 8 receive ? shift ? registers receive ? buffer ? registers 0, ? 1 ? (rxb0, ? rxb1) 8 transmit ? control parity ? addition receive ? control parity ? check transmit ? shift ? registers tmx ? output remark tmx output is as follows: uart0: tm3 uart1: tm2 (1) transmit shift registers 0, 1 (txs0, txs1) txsn is the register for setting transmit data. data written to txsn is transmitted as serial data. when the data length is set to 7 bits, bit 0 to bit 6 of the dat a written to txsn is transmitt ed as serial data. writing data to txsn starts the transmit operation. txsn can be written to by an 8-bit memory m anipulation instruction. it cannot be read from. reset input sets these registers to ffh. caution do not write to txsn during a transmit operation. (2) receive shift registers 0, 1 (rx0, rx1) the rxn register converts serial dat a input via the rxd0 and rxd1 pins in to parallel data. when one byte of data is received at rxn, the receiv ed data is transferred to receive buffer registers 0 and 1 (rxb0, rxb1). rx0 and rx1 cannot be manipulated directly by a program. (3) receive buffer registers 0, 1 (rxb0, rxb1) rxbn is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred. when the data length is set to 7 bits, re ceived data is sent to bit 0 to bit 6 of rxbn. in rxbn, the msb must be set to 0. rxbn can be read by an 8-bit memory manipulat ion instruction. it cannot be written to. reset input sets rxbn to ffh.
chapter 10 serial interface function user?s manual u12768ej4v1ud 288 (4) transmission controller the transmission controller controls tr ansmit operations, such as adding a star t bit, parity bit, and stop bit to data that is written to transmit shift regi ster n (txsn), based on the values set to asynchronous serial interface mode register n (asimn). (5) reception controller the reception controller controls re ceive operations based on the values se t to asynchronous serial interface mode register n (asimn). during a re ceive operation, it performs error che cking, such as for parity errors, and sets various values to asynchronous serial interface status register n (asisn) according to the type of error that is detected. 10.4.2 uartn control registers uartn uses the following four types of registers for control functions (n = 0, 1). asynchronous serial interface mode register n (asimn) asynchronous serial interfac e status register n (asisn) baud rate generator cont rol register n (brgcn) baud rate generator mode control r egisters n and 01 (brgmcn, brgmc01) (1) asynchronous serial interface mode registers 0, 1 (asim0, asim1) asimn is an 8-bit register that controls the serial transfer operations of uartn. asimn can be set by an 8-bit or 1-bi t memory manipulation instruction. reset input sets these registers to 00h.
chapter 10 serial interface function user?s manual u12768ej4v1ud 289 after reset: 00h r/w address: fffff300h, fffff310h 7 6 5 4 3 2 1 0 asimn txen rxen ps1n ps0n ucln sln isrmn 0 (n = 0, 1) txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stop port function port function 0 1 uart mode (receive only) se rial function port function 1 0 uart mode (transmit only) port function serial function 1 1 uart mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity ucln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 0 1 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs cautions 1. do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. be sure to set bit 0 to 0.
chapter 10 serial interface function user?s manual u12768ej4v1ud 290 (2) asynchronous serial interface status registers 0, 1 (asis0, asis1) when a receive error occurs in uart mode, t hese registers indicate the type of error. asisn can be read using an 8-bit or 1-bi t memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r address: fffff302h, fffff312h 7 6 5 4 3 2 1 0 asisn 0 0 0 0 0 pen fen oven (n = 0, 1) pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if the stop bit length has been set to two bits by setting bit 2 (sln) of asynchronous serial interface mode register n (asimn ), stop bit detection during a re ceive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive buffe r register n (rxbn) when an overrun error has occurred. until the contents of rxbn are read, further overrun errors will occur when receiving data.
chapter 10 serial interface function user?s manual u12768ej4v1ud 291 (3) baud rate generator control registers 0, 1 (brgc0, brgc1) these registers set the serial clock for uartn. brgcn can be set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: fffff304h, fffff314h 7 6 5 4 3 2 1 0 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 (n = 0, 1) md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 selection of input clock k 0 0 0 0 0 setting prohibited ? 0 0 0 0 1 0 0 0 f sck /8 8 0 0 0 0 1 0 0 1 f sck /9 9 0 0 0 0 1 0 1 0 f sck /10 10 0 0 0 0 1 0 1 1 f sck /11 11 0 0 0 0 1 1 0 0 f sck /12 12 0 0 0 0 1 1 0 1 f sck /13 13 0 0 0 0 1 1 1 0 f sck /14 14 0 0 0 0 1 1 1 1 f sck /15 15 0 0 0 1 0 0 0 0 f sck /16 16 1 1 1 1 1 1 1 1 f sck /255 255 cautions 1. the value of brgcn becomes 00h afte r reset. before starting operation, select a setting other than ?setting prohibited?. selecting the ?setting prohibited? setting in stop mode does not cause any problems. 2. if write is performed to brgcn during communication processing, the output of the baud rate generator will be dist urbed and communication will not be performed normally. therefore, do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter
chapter 10 serial interface function user?s manual u12768ej4v1ud 292 (4) baud rate generator mode control registers 0, 01 (brgmc0, brgmc01) these registers set the uartn source clock. brgmc0 and brgmc01 are set by an 8-bi t memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: fffff320h 7 6 5 4 3 2 1 0 brgmc01 0 0 0 0 0 0 0 tps03 after reset: 00h r/w address: fffff30eh 7 6 5 4 3 2 1 0 brgmc0 0 0 0 0 0 tps02 tps01 tps00 tps03 tps02 tps01 tps00 8-bit counter source clock selection m 0 0 0 0 external clock (asck0) ? 0 0 0 1 f xx 0 0 0 1 0 f xx /2 1 0 0 1 1 f xx /4 2 0 1 0 0 f xx /8 3 0 1 0 1 f xx /16 4 0 1 1 0 f xx /32 5 0 1 1 1 tm3 output ? 1 0 0 0 f xx /64 6 1 0 0 1 f xx /128 7 1 0 1 0 f xx /256 8 1 0 1 1 f xx /512 9 1 1 0 0 ? 1 1 0 1 ? 1 1 1 0 ? 1 1 1 1 setting prohibited ? cautions 1. if write is performed to brgmc0, brgmc01 during communication processing, the output of the baud rate generator will be disturbed and communi cation will not be performed normally. therefore, do not write to brgmc0, brgmc01 during communication processing. 2. be sure to set bits 3 to 7 of the brgmc0 register to 0. remarks 1. source clock of 8-bit counter: f sck 2. when the selected clock is the timer output, it is not necessary to set the p27/ti3/to3 pin to timer output mode.
chapter 10 serial interface function user?s manual u12768ej4v1ud 293 (5) baud rate genera tor mode control register 1 (brgmc1) this register sets the uart1 source clock. brgmc1 is set by an 8-bit memory manipulation instruction. reset input sets this register to 00h. after reset: 00h r/w address: fffff31eh 7 6 5 4 3 2 1 0 brgmc1 0 0 0 0 0 tps12 tps11 tps10 tps12 tps11 tps10 8-bit counter source clock selection m 0 0 0 external clock (asck1) ? 0 0 1 f xx 0 0 1 0 f xx /2 1 0 1 1 f xx /4 2 1 0 0 f xx /8 3 1 0 1 f xx /16 4 1 1 0 f xx /32 5 1 1 1 tm2 output ? cautions 1. if write is performed to brgmc1 during communication processing, the output of the baud rate generator will be dist urbed and communication will not be performed normally. therefore, do not write to brgmc 1 during communication processing. 2. be sure to set bits 3 to 7 to 0. remarks 1. source clock of 8-bit counter: f sck 2. when the selected clock is timer the output, it is not necessary to set the p26/ti2/to2 pin to timer output mode.
chapter 10 serial interface function user?s manual u12768ej4v1ud 294 10.4.3 operations uartn has the following two operation modes. operation stop mode asynchronous serial interface (uart) mode (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. in operation stop mode, pins can be used as normal ports. (a) register settings operation stop mode settings are made via the txen and rxen bits of a synchronous serial interface mode register n (asimn). figure 10-24. settings of asimn (operation stop mode) after reset: 00h r/w address: fffff300h, fffff310h 7 6 5 4 3 2 1 0 asimn txen rxen ps1n ps0n cln sln isrmn 0 (n = 0, 1) txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stop port function port function cautions 1. do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. be sure to set bit 0 to 0.
chapter 10 serial interface function user?s manual u12768ej4v1ud 295 (2) asynchronous serial interface (uart) mode this mode enables full-duplex operation in which one byte of data is transmitted and received after the start bit. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (a) register settings uart mode settings are made via asynchronous serial interface mode register n (asimn), asynchronous serial interface status register n (asisn), baud rate generator control r egister n (brgcn), baud rate generator mode control registers n and 01 (brg mcn, brgmc01) (n = 0, 1). figure 10-25. asimn setting (uart mode) after reset: 00h r/w address: fffff300h, fffff310h 7 6 5 4 3 2 1 0 asimn txen rxen ps1n ps0n cln sln isrmn 0 (n = 0, 1) txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 1 uart mode (receive only) se rial function port function 1 0 uart mode (transmit only) port function serial function 1 1 uart mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 0 1 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs cautions 1. do not switch the operation mode until after the curre nt serial transmit/receive operation has stopped. 2. be sure to set bit 0 to 0.
chapter 10 serial interface function user?s manual u12768ej4v1ud 296 figure 10-26. asisn setting (uart mode) after reset: 00h r address: fffff302h, fffff312h 7 6 5 4 3 2 1 0 asisn 0 0 0 0 0 pen fen oven (n = 0, 1) pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if the stop bit length has been set to two bits by setting bit 2 (sln) of asynchronous serial interface mode register n (asimn ), stop bit detection during a re ceive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive bu ffer register n (rxbn) when an overrun error has occurred. until the contents of the rxbn register are read, further ove rrun errors will occur when receiving data.
chapter 10 serial interface function user?s manual u12768ej4v1ud 297 figure 10-27. brgcn setting (uart mode) after reset: 00h r/w address: fffff304h, fffff314h 7 6 5 4 3 2 1 0 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 (n = 0, 1) md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 input clock selection k 0 0 0 0 0 setting prohibited ? 0 0 0 0 1 0 0 0 f sck /8 8 0 0 0 0 1 0 0 1 f sck /9 9 0 0 0 0 1 0 1 0 f sck /10 10 0 0 0 0 1 0 1 1 f sck /11 11 0 0 0 0 1 1 0 0 f sck /12 12 0 0 0 0 1 1 0 1 f sck /13 13 0 0 0 0 1 1 1 0 f sck /14 14 0 0 0 0 1 1 1 1 f sck /15 15 0 0 0 1 0 0 0 0 f sck /16 16 1 1 1 1 1 1 1 1 f sck /255 255 cautions 1. reset input sets the brgcn register to 00h. before starting operation, select a se tting other than ?setting prohibited?. selecting a ?setting prohibited? se tting in stop mode does not cause any problems. 2. if write is performed to the brgcn register during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. therefore , do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter
chapter 10 serial interface function user?s manual u12768ej4v1ud 298 figure 10-28. brgmc0 and brgmc01 settings (uart mode) after reset: 00h r/w address: fffff30eh 7 6 5 4 3 2 1 0 brgmc0 0 0 0 0 0 tps02 tps01 tps00 after reset: 00h r/w address: fffff320h 7 6 5 4 3 2 1 0 brgmc01 0 0 0 0 0 0 0 tps03 tps03 tps02 tps01 tps00 8-bit c ounter source clock selection m 0 0 0 0 external clock (asck0) ? 0 0 0 1 f xx 0 0 0 1 0 f xx /2 1 0 0 1 1 f xx /4 2 0 1 0 0 f xx /8 3 0 1 0 1 f xx /16 4 0 1 1 0 f xx /32 5 0 1 1 1 tm3 output ? 1 0 0 0 f xx /64 6 1 0 0 1 f xx /128 7 1 0 1 0 f xx /256 8 1 0 1 1 f xx /512 9 1 1 0 0 ? 1 1 0 1 ? 1 1 1 0 ? 1 1 1 1 setting prohibited ? cautions 1. if write is performed to the brgmc0 and brgmc01 registers during communication processing, the output of the baud rate generator is disturbed and communication will not be performed norma lly. therefore, do not write to the brgmc0 and brgmc01 registers dur ing communication processing. 2. be sure to set bits 3 to 7 of the brgmc0 register to 0. remarks 1. f xx : main clock oscillation frequency 2. when the timer output is selected as the clock, it is not necessary to set the p27/to3/ti3 pin to timer output mode.
chapter 10 serial interface function user?s manual u12768ej4v1ud 299 figure 10-29. brgmc1 settings (uart mode) after reset: 00h r/w address: fffff31eh 7 6 5 4 3 2 1 0 brgmc1 0 0 0 0 0 tps12 tps11 tps10 tps12 tps11 tps10 8-bit counter source clock selection m 0 0 0 external clock (asck1) ? 0 0 1 f xx 0 0 1 0 f xx /2 1 0 1 1 f xx /4 2 1 0 0 f xx /8 3 1 0 1 f xx /16 4 1 1 0 f xx /32 5 1 1 1 tm2 output ? cautions 1. if write is performed to the brgmc1 register during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. there fore, do not write to the brgmc1 register during communication processing. 2. be sure to set bits 3 to 7 of to 0. remarks 1. f xx : main clock oscillation frequency 2. when the timer output is selected as the clock, it is not necessary to set the p26/to2/ti2 pin to timer output mode.
chapter 10 serial interface function user?s manual u12768ej4v1ud 300 (b) baud rate the transmit/receive clock for the baud rate to be generat ed is a signal generated by dividing the main clock. ? generation of baud rate transm it/receive clock using main clock the transmit/receive clock is obtained by dividing the main clock. the following equation is used to obtain the baud rate from the main clock. [baud rate] = [hz] f xx : main clock oscillation frequency m: value set by tps03 to tps00 (0 m 9) ? when uart0 value set by tps12 to tps10 (0 m 5) ? when uart1 k: value set by mdln7 to mdln0 (8 k 255) baud rate error tolerance the baud rate error tolerance depends on the number of bits in a frame and the counter division ratio [1/(16+k)]. table 10-8 shows the relationship between the ma in clock and the baud rate, and figure 10-30 shows an example of the baud rate error tolerance. f xx 2 m+1 k
chapter 10 serial interface function user?s manual u12768ej4v1ud 301 table 10-8. relationship betw een main clock and baud rate f xx = 2 mhz f xx = 4.194 mhz f xx = 8.388 mhz f xx = 17 mhz f xx = 20 mhz baud rate (bps) k m error (%) k m error (%) k m error (%) k m error (%) k m error (%) 255 9 ? 4.26 ? ? ? ? ? ? ? ? ? ? ? ? 16 244 8 0.06 255 9 0.39 ? ? ? ? ? ? ? ? ? 32 244 7 0.06 255 8 0.38 255 9 0.38 ? ? ? ? ? ? 75 208 6 0.16 218 7 0.20 218 8 0.20 221 9 0.16 ? ? ? 76 206 6 ? 0.20 216 7 ? 0.20 216 8 ? 0.20 218 9 0.20 255 9 0.78 256 244 4 0.06 128 6 0.01 128 7 0.01 130 8 ? 0.23 152 8 0.39 1200 208 2 0.16 217 3 0.20 217 4 0.20 221 5 0.16 130 6 0.16 2400 208 1 0.16 218 2 0.20 218 3 0.20 221 4 0.16 130 5 0.16 4800 208 0 0.16 218 1 0.20 218 2 0.20 221 3 0.16 130 4 0.16 9600 104 0 0.16 218 0 0.20 218 1 0.20 221 2 0.16 130 3 0.16 19200 52 0 0.16 109 0 0.20 218 0 0.20 221 1 0.16 130 2 0.16 31250 32 0 0.00 67 0 0.16 134 0 0.16 136 1 0.00 160 1 0.00 38400 26 0 0.16 55 0 ? 0.71 110 0 ? 0.71 221 0 0.16 130 1 0.16 76800 13 0 0.16 27 0 1.13 54 0 1.13 111 0 ? 0.29 130 0 0.16 125000 8 0 0.00 17 0 ? 1.32 34 0 ? 1.32 68 0 0.00 80 0 0.00 150000 ? ? ? 14 0 0.14 28 0 0.14 55 0 0.62 67 0 ? 0.50 262000 ? ? ? 8 0 0.05 16 0 0.05 32 0 1.38 38 0 0.44 300000 ? ? ? ? ? ? 14 0 ? 0.14 28 0 ? 1.18 33 0 1.01 524000 ? ? ? ? ? ? 8 0 0.05 16 0 1.38 19 0 0.44 1250000 ? ? ? ? ? ? ? ? ? 7 0 ? 2.86 8 0 0.00 remark fxx: main clock oscillation frequency figure 10-30. error tolerance (when k = 16), including sampling errors remark t: 8-bit counter?s source clock cycle baud rate error tolerance (when k = 16) = 100 = 4.8438 (%) basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t 15.5 320
chapter 10 serial interface function user?s manual u12768ej4v1ud 302 (c) communication operations (i) data format as shown in figure 10-31, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. asynchronous serial interface mode regi ster n (asimn) is used to set the c haracter bit length, parity selection, and stop bit length within each data frame (n = 0, 1). figure 10-31. format of transmit/receive da ta in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame start bit ............. 1 bit character bits ... 7 bits or 8 bits parity bit ........... even parity, odd parity, ze ro parity, or no parity stop bit(s) ........ 1 bit or 2 bits when 7 bits is selected as the number of character bits, only the lower 7 bits (from bit 0 to bit 6) are valid, so that during a transmission the highest bi t (bit 7) is ignored and during recept ion the highest bit (bit 7) must be set to 0. asynchronous serial interface mode register n (asi mn) and baud rate generator cont rol register n (brgcn) are used to set the serial transfer rate (n = 0, 1). if a receive error occurs, information about the rece ive error can be ascertained by reading asynchronous serial interface status register n (asisn) (n = 0, 1).
chapter 10 serial interface function user?s manual u12768ej4v1ud 303 (ii) parity types and operations the parity bit is used to detect bit errors in transfer dat a. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or ev en parity is set, errors in the parity bit (the odd- number bit) can be detected. when zero parity or no parity is set, errors are not detected. <1> even parity during transmission the number of bits in transmit data including the parity bit is cont rolled so that an even number of ?1? bits is set. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?1? if the transmit data contains an even number of ?1? bits: the parity bit value is ?0? during reception the number of ?1? bits is c ounted among the receive data includi ng a parity bit, and a parity error occurs when the result is an odd number. <2> odd parity during transmission the number of bits in transmit data including a par ity bit is controlled so that an odd number of ?1? bits is set. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?0? if the transmit data contains an even number of ?1? bits: the parity bit value is ?1? during reception the number of ?1? bits is c ounted among the receive data includi ng a parity bit, and a parity error occurs when the result is an even number. <3> zero parity during transmission, the parity bit is set to ?0? regardless of the transmit data. during reception, the parity bit is not checked. theref ore, no parity errors will occur regardless of whether the parity bit is a ?0? or a ?1?. <4> no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. sinc e there is no parity bit, no parity errors will occur.
chapter 10 serial interface function user?s manual u12768ej4v1ud 304 (iii) transmission the transmit operation is started when tr ansmit data is written to transmit shift register n (txsn). a start bit, parity bit, and stop bit(s) are aut omatically added to the data. starting the transmit operation shifts out the data in txsn, thereby em ptying txsn, after which a transmit completion interrupt (intstn) is issued. the timing of the transmit completion interrupt is shown below. figure 10-32. timing of asynchronous serial interface transmit completion interrupt caution do not write to asynchronous serial interf ace mode register n (asimn) during a transmit operation. writing to asimn during a transm it operation may disable further transmit operations (in such cases, input reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (intstn) or th e interrupt request flag (stifn) that is set by intstn. remark n = 0, 1 txdn (output) d0 d1 d2 d6 d7 parity stop start intstn (a) stop bit length: 1 txdn (output) d0 d1 d2 d6 d7 parity start intstn (b) stop bit length: 2 stop
chapter 10 serial interface function user?s manual u12768ej4v1ud 305 (iv) reception the receive operation is enabled when ?1? is set to bi t 6 (rxen) of asynchronous serial interface mode register n (asimn), and the input via the rxdn pin is sampled. the serial clock specified by baud rate generator c ontrol register n (brgcn) is used when sampling the rxdn pin. when the rxdn pin goes low, the 5- bit counter begins counting and the st art timing signal for data sampling is output when half of the s pecified baud rate time has elapsed. if samp ling the rxdn pin input with this start timing signal yields a low-level result, a start bit is re cognized, after which the 5- bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is co mpleted, the receive data in the shi ft register is transferred to receive buffer register n (rxbn) and a receive co mpletion interrupt (intsrn) occurs. even if an error has occurred, the receive data in wh ich the error occurred is still transferred to rxbn. when an error occurs, instrn is generated if bit 1 (isr mn) of asimn is cleared (0 ). on the other hand, intsrn is not generated if the isrmn bit is set (1) (see 10.4.2 (1) asynchronous serial interface mode registers 0 and 1 (asim0, asim1 ). if the rxen bit is reset to 0 during a receive operation, the receive operation is st opped immediately. at this time, the contents of rxbn and asisn do not change, nor does intsrn or intsern occur. the timing of the asynchronous serial interface receive completion interrupt is shown below. figure 10-33. timing of asynchronous seri al interface receive completion interrupt caution be sure to read the contents of r eceive buffer register n (r xbn) even when a receive error has occurred. if the contents of rxbn are not r ead, an overrun error will occur during the next data receive operation a nd the receive error status will remain. remarks 1. n = 0, 1 2. the interrupt control register of intsr0 is alternately used as the interrupt control register (csic1) of intcsi1. an sric0 register does not exist. rxdn (input) d0 d1 d2 d6 d7 parity stop start intsrn
chapter 10 serial interface function user?s manual u12768ej4v1ud 306 (v) receive error three types of errors can occur during a receive operati on: a parity error, framing error, and overrun error. when, as the result of data reception, an error flag is set in asynchr onous serial interface status register n (asisn), the receive error interrupt request (intsern) is gener ated. the receive error interrupt request is generated prior to the receive completion interrupt reques t (intsrn). table 10-9 shows receive error causes. by reading the contents of asi sn during receive error interrupt servici ng (intsern), it is possible to ascertain which error has occurred during reception (see table 10-9 and 10.4.2 (2) asynchronous serial interface status registers 0 and 1 (asis0, asis1) the contents of asisn are reset (0 ) by reading the receive buffer regi ster (rxbn) or receiving subsequent data (if there is an error in the s ubsequent data, the error flag is set). table 10-9. receive error causes receive error cause asisn value parity error parity specific ation at transmission and receive data parity do not match. 04h framing error stop bit is not detected. 02h overrun error reception of subsequent data wa s completed before data was read from the receive buffer register. 01h figure 10-34. receive error timing note even if a receive error occurs when the isrmn bi t of asimn is set (1), intsrn is not generated. cautions 1. the contents of asyn chronous serial interface status re gister n (asisn) are reset (0) by reading receive buffer register n (rxb n) or receiving subsequent data. to check the contents of an error, always read asisn before reading rxbn. 2. be sure to read recei ve buffer register n (rxbn) even when a receive error occurs. if rxbn is not read out, an overrun error will occur during subsequent data reception and as a result receive e rrors will continue to occur. remark n = 0, 1 start d0 rxdn (input) intsrn note intsern intsern (when parity error occurs) d1 d2 d6 d7 stop parity
chapter 10 serial interface function user?s manual u12768ej4v1ud 307 10.4.4 standby function (1) operation in halt mode only serial transfer operations are performed normally. (2) operation in idle and software stop modes (a) when internal clock is selected as serial clock the operations of asynchronous serial interface mode register n (asimn), a synchronous serial status register n (asisn), baud rate generator contro l register n (brgcn), baud rage gener ator mode control registers n and 01 (brgmcn, brgmc01), transmit shift register n (t xsn), and receive buffer register n (rxbn) are stopped and their values immediately bef ore the clock stopped are held. the txdn pin output holds the dat a immediately before the clock wa s stopped (in software stop mode) during transmission. when the clock is stopped during re ception, the receive dat a until the clock stopped is stored and subsequent receive operat ions are stopped. reception resumes upon clock restart. (b) when external clock is selected as serial clock only serial transfer operations are performed normally.
user?s manual u12768ej4v1ud 308 chapter 11 a/d converter 11.1 function the a/d converter converts analog input signals into digital values with a resolution of 10 bits, and can handle 12 channels of analog input signals (ani0 to ani11). (1) hardware start conversion is started by trigger input (adtrg) (rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting the a/d converter mode register (adm). one analog input channel is selected from ani0 to ani11, and a/d conversion is performed. if a/d conversion has been started by means of har dware start, conversion stops once it has been completed, and an interrupt request (intad) is generated. if conversion has been started by means of software star t, conversion is performed repeatedly. each time conversion has been co mpleted, intad is generated. operation of the a/d converte r continues in halt mode.
chapter 11 a/d converter user?s manual u12768ej4v1ud 309 the block diagram is shown below. figure 11-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 av ref av dd av ss intad 4 ads3 ads2 ads1 ads0 adcs trg fr2 fr1 fr0 ega1 ega0 adps selector sample & hold circuit av ss voltage comparator tap selector adtrg edge detector controller a/d conversion result register (adcr) trigger enable analog input channel specification register (ads) a/d converter mode register (adm) internal bus successive approximation register (sar)
chapter 11 a/d converter user?s manual u12768ej4v1ud 310 11.2 configuration the a/d converter consists of the following hardware. table 11-1. configuration of a/d converter item configuration analog input 12 channels (ani0 to ani11) registers successive approxim ation register (sar) a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read control registers a/d converter mode register (adm) analog input channel specif ication register (ads) (1) successive approximation register (sar) this register compares the voltage value of the analog input signal with t he voltage tap (compare voltage) value from the series resistor string, and holds the result of the comparison starting from the most significant bit (msb). when the comparison result has been stor ed down to the least significant bit (lsb) (i.e., when the a/d conversion has been completed), the contents of the sar are transferred to the a/ d conversion result register. (2) a/d conversion result register (adcr), a/d conversion result register h (adcrh) each time a/d conversion is completed, the result of the conver sion is loaded to this register from the successive approximation register. the higher 10 bits of this register hold the result of the a/d conversion (the lower 6 bits are fixed to 0). this register is read using a 16-bit me mory manipulation instruction. reset input sets adcr to 0000h. when using only the higher 8 bits of the result of the a/d conversion, adcrh is read using an 8-bit memory manipulation instruction. reset input sets adcrh to 00h. (3) sample & hold circuit the sample & hold circuit samples each of the analog i nput signals sequentially sent from the input circuit, and sends the sampled data to the voltage co mparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (4) voltage comparator the voltage comparator compar es the analog input signal with the output voltage of the se ries resistor string. (5) series resistor string the series resistor st ring is connected between av ref and av ss and generates a voltage fo r comparison with the analog input signal.
chapter 11 a/d converter user?s manual u12768ej4v1ud 311 (6) ani0 to ani11 pins these are analog input pins for the 12 channels of the a/d converter, and are used to input analog signals to be converted into digital signals. pi ns other than ones select ed as the analog input by the analog input channel specification register (ads ) can be used as input ports. caution make sure that the volt ages input to ani0 through ani11 do not exceed the rated values. if a voltage higher than or equal to av ref or lower than or equal to av ss (even within the range of the absolute maximum ratings) is input to a channel, the conver sion value of the channel is undefined, and the conversion values of the other channels may also be affected. (7) av ref pin this pin inputs a reference vo ltage to the a/d converter. the signals input to the ani0 through ani11 pins are converted into digital signals based on the voltage applied across av ref and av ss . (8) av ss pin this is the ground pin of the a/d converter. always keep the potential at this pin t he same as that at the v ss pin even when the a/d converter is not in use. (9) av dd pin this is the analog power supply pin of t he a/d converter. always k eep the potential at this pi n the same as that at the v dd pin even when the a/d converter is not in use.
chapter 11 a/d converter user?s manual u12768ej4v1ud 312 11.3 control registers the a/d converter is controll ed by the following registers. ? a/d converter mode register (adm) ? analog input channel specif ication register (ads) (1) a/d converter mode register (adm) this register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger. adm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adm to 00h. (1/2) after reset: 00h r/w address: fffff3c0h 7 6 5 4 3 2 1 0 adm adcs trg fr2 fr1 fr0 ega1 ega0 adps adcs a/d conversion control 0 conversion stopped 1 conversion enabled trg software start or hardware start selection 0 software start 1 hardware start
chapter 11 a/d converter user?s manual u12768ej4v1ud 313 (2/2) adps fr2 fr1 fr0 selection of conversion time note 1 + stabilization time note 2 0 0 0 0 288/f xx 0 0 0 1 216/f xx 0 0 1 0 168/f xx 0 0 1 1 120/f xx 0 1 0 0 96/f xx 0 1 0 1 72/f xx 0 1 1 0 60/f xx 0 1 1 1 48/f xx 1 0 0 0 288/f xx + 144/f xx 1 0 0 1 216/f xx + 108/f xx 1 0 1 0 168/f xx + 84/f xx 1 0 1 1 120/f xx + 60/f xx 1 1 0 0 96/f xx + 48/f xx 1 1 0 1 72/f xx + 36/f xx 1 1 1 0 60/f xx + 30/f xx 1 1 1 1 48/f xx + 24/f xx ega1 ega0 edge specification for external trigger signal 0 0 no edge detection 0 1 detection at falling edge 1 0 detection at rising edge 1 1 detection at both rising and falling edges adps a/d conversion time mode selection 0 comparator on 1 comparator off notes 1. conversion time (actual a/d conversion time) always set the time to 5 s conversion time 100 s. however, when adps bit = 1, the oscillation stabilization time is not included. 2. stabilization time (setup time of a/d converter) each a/d conversion requires ?conversion time + stab ilization time?. there is no stabilization time when adps = 0. remark turning off the internal comparator cuts the current flowing through the av dd pin.
chapter 11 a/d converter user?s manual u12768ej4v1ud 314 table 11-2. a/d conversion time selection conversion time selection f xx adps fr2 fr1 fr0 conversion time + stabilization time 20 mhz 17 mhz 13.5 mhz 8 mhz 2 mhz 0 0 0 0 288/f xx 14.4 s 16.9 s 21.3 s 36.0 s setting prohibited 0 0 0 1 216/f xx 10.8 s 12.7 s 16.0 s 27.0 s setting prohibited 0 0 1 0 168/f xx 8.4 s 9.9 s 12.4 s 21.0 s 84.0 s 0 0 1 1 120/f xx 6.0 s 7.1 s 8.9 s 15.0 s 60.0 s 0 1 0 0 96/f xx setting prohibited 5.6 s 7.1 s 12.0 s 48.0 s 0 1 0 1 72/f xx setting prohibited setting prohibited 5.3 s 9.0 s 36.0 s 0 1 1 0 60/f xx setting prohibited setting prohibited setting prohibited 7.5 s 30.0 s 0 1 1 1 48/f xx setting prohibited setting prohibited setting prohibited 6.0 s 24.0 s 1 0 0 0 288/f xx +144/f xx 21.6 s 25.4 s 32.0 s 54.0 s setting prohibited 1 0 0 1 216/f xx +108/f xx 16.2 s 19.1 s 24.0 s 40.5 s setting prohibited 1 0 1 0 168/f xx +84/f xx 12.6 s 14.9 s 18.7 s 31.5 s setting prohibited 1 0 1 1 120/f xx +60/f xx 9.0 s 10.7 s 13.3 s 22.5 s 90.0 s 1 1 0 0 96/f xx +48/f xx setting prohibited 8.4 s 10.7 s 18.0 s 72.0 s 1 1 0 1 72/f xx +36/f xx setting prohibited setting prohibited 8.0 s 13.5 s 54.0 s 1 1 1 0 60/f xx +30/f xx setting prohibited setting prohibited setting prohibited 11.3 s 45.0 s 1 1 1 1 48/f xx +24/f xx setting prohibited setting prohibited setting prohibited 9.0 s 36.0 s
chapter 11 a/d converter user?s manual u12768ej4v1ud 315 (2) analog input channel specification register (ads) ads specifies the port for inputting the analog vo ltage to be converted into a digital signal. ads is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets ads to 00h. after reset: 00h r/w address: fffff3c2h 7 6 5 4 3 2 1 0 ads 0 0 0 0 ads3 ads2 ads1 ads0 ads3 ads2 ads1 ads0 analog input channel specification 0 0 0 0 ani0 0 0 0 1 ani1 0 0 1 0 ani2 0 0 1 1 ani3 0 1 0 0 ani4 0 1 0 1 ani5 0 1 1 0 ani6 0 1 1 1 ani7 1 0 0 0 ani8 1 0 0 1 ani9 1 0 1 0 ani10 1 0 1 1 ani11 other than above setting prohibited caution be sure to set bits 4 to 7 to 0.
chapter 11 a/d converter user?s manual u12768ej4v1ud 316 11.4 operation 11.4.1 basic operation <1> select one channel whose analog signal is to be conver ted into a digital signal by using the analog input channel specification register (ads). <2> the sample & hold circuit samples the vo ltage input to the selected analog input channel. <3> after sampling for a specific time, the sample & hol d circuit enters the hold stat us, and holds the input analog voltage until it has been converted into a digital signal. <4> set bit 9 of the successive approximation register (sar). the tap selector sets t he voltage tap of the series resistor string to (1/2) av ref . <5> the voltage difference between the voltage tap of the series resistor string and the analog input voltage is compared by the voltage compar ator. if the analog input volt age is greater than (1/2) av ref , the msb of the sar remains set. if the analog input voltage is less than (1/2) av ref , the msb is reset. <6> next, bit 8 of the sar is automatically set, and the analog input voltage is compared again. depending on the value of bit 9 to which the re sult of the preceding co mparison has been set, the vo ltage tap of the series resistor string is selected as follows: ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the analog input voltage is compared wit h one of these voltage taps, and bit 8 of the sar is manipulated as follows depending on the result of the comparison. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage voltage tap: bit 8 = 0 <7> the above steps are r epeated until bit 0 of the sar has been manipulated. <8> when comparison of all 10 bits of the sar has been co mpleted, the valid digital value remains in the sar, and the value of the sar is transferred and latched to the a/d conversion result register (adcr). at the same time, an a/d conversion end interrupt request (int ad) can be generated. caution the first conversion value immediately after setting adcs = 0 1 may not satisfy the ratings.
chapter 11 a/d converter user?s manual u12768ej4v1ud 317 figure 11-2. basic operation of a/d converter a/d conversion is successively executed until bit 7 (adcs) of the a/d converter mode register (adm) is reset to 0 by software. if adm and the analog input channel specific ation register (ads) are written dur ing a/d conversion, the conversion is initialized. if adcs is set to 1 at this time, conversion is star ted from the beginning. reset input sets the a/d conversi on result register (adcr) to 0000h. sar adcr intad conversion time sampling time sampling operation of a/d converter a/d conversion undefined conversion result conversion result
chapter 11 a/d converter user?s manual u12768ej4v1ud 318 11.4.2 input voltage and conversion result the analog voltages input to the analog i nput pins (ani0 to ani11) and the re sult of the a/d conversion (contents of the a/d conversion result regist er (adcr)) are related as follows. adcr = int( 1024 + 0.5) or, (adcr ? 0.5) v in < (adcr + 0.5) int ( ): function that returns integer of value in ( ) v in : analog input voltage av ref : av ref pin voltage adcr: value of the a/d conver sion result register (adcr) the relationship between the anal og input voltage and a/d conversi on result is shown below. figure 11-3. relationship between analog i nput voltage and a/d conversion result v in av ref av ref 1024 av ref 1024 113253 2043 1022 20451023 2047 1 2048 1024 20481024 2048 1024 2048 1024 20481024 2048 0 1 2 3 1021 1022 1023 a/d conversion result (adcr) input voltage/av ref
chapter 11 a/d converter user?s manual u12768ej4v1ud 319 11.4.3 a/d converter operation mode in this mode one of the analog input channels ani0 to ani 11 is selected by the analog input channel specification register (ads) and a/d c onversion is executed. the a/d conversion can be start ed in the following two ways. ? hardware start: started by trigger input (adtrg ) (rising edge, falling edge, or both rising and falling edges can be specified) ? software start: started by setting a/ d converter mode register (adm) the result of the a/d conv ersion is stored in the a/d conversion resu lt register (adcr) and an interrupt request signal (intad) is generated at the same time.
chapter 11 a/d converter user?s manual u12768ej4v1ud 320 (1) a/d conversion by hardware start a/d conversion is on standby if bit 6 (t rg) and bit 7 (adcs) of the a/d conver ter mode register (adm) are set to 1. when an external trigger signal is input, the a/d c onverter starts converting t he voltage applied to the analog input pin specified by the analog i nput channel specification register (ads) into a digital signal. when a/d conversion has been completed, the result of the conversion is st ored in the a/d conversion result register (adcr), and an interrupt reques t signal (intad) is generated. once in a/d conversion has been started and completed, conversion is not started again unless a new external trigger signal is input. if data with adcs set to 1 is written to adm during a/ d conversion, the conversi on under execution is stopped, and the a/d converter stands by until a new external trigger signal is input. if the external trigger signal is input, a/d conversion is executed again from the beginning. if data with adcs set to 0 is written to adm during a/ d conversion, the conversi on is immediately stopped. caution be sure to make the input interval of the external trigger si gnal higher than the conversion time specified by the fr2 to fr0 bits of the adm register + 6 cpu clocks. figure 11-4. a/d conversion by hardwa re start (with falling edge specified) remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11 rewriting ads adcs = 1, trg = 1 rewriting ads adcs = 1, trg = 1 a/d conversion adcr intad anin standby status standby status standby status anin anin anim anim anim anin anin anin anim anim external trigger input signal
chapter 11 a/d converter user?s manual u12768ej4v1ud 321 (2) a/d conversion by software start if bit 6 (trg) of a/d converter mode regi ster 1 (adm1) is set to 0 and bit 7 (a dcs) is set to 1, the a/d converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ads) into a digital signal. when a/d conversion has been completed, the result of the conversion is st ored in the a/d conversion result register (adcr), and an interrupt reques t signal (intad) is generated. on ce a/d conversion has been started and completed, the next conversion is st arted immediately. a/d conversion is repeated until new data is written to ads. if ads is rewritten during a/d conver sion, the conversion under execution is stopped, and c onversion of the newly selected analog input channel is started. if data with adcs set to 0 is written to adm during a/ d conversion, the conversi on is immediately stopped. figure 11-5. a/d conversion by software start remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11 rewriting ads adcs = 1, trg = 0 rewriting ads adcs = 1, trg = 0 adcs = 0 a/d conversion adcr intad anin anin anin anim anim anin anin anim conversion stopped. conversion result does not remain. stopped
chapter 11 a/d converter user?s manual u12768ej4v1ud 322 11.5 notes on using a/d converter (1) current consumpti on in standby mode the a/d converter stops operation in t he idle/software stop mode (operable in the halt mode). at this time, the current consumption of the a/d converter can be reduced by stopping the conver sion (by resetting the bit 7 (adcs) of the a/d converter mode register (adm) to 0). to reduce the current consumption in t he idle/software stop mode, set the av ref potential in the user circuit to the same value (0 v) as the av ss potential. (2) input range of ani0 to ani11 keep the input voltage of the ani0 thr ough ani11 pins to within the rated r ange. if a voltage greater than or equal to av ref or lower than or equal to av ss (even within the range of the absolute maximum ratings) is input to a channel, the converted value of the c hannel becomes undefined. moreover, t he values of the other channels may also be affected. (3) conflict <1> conflict between writing a/d conversion result register (adcr) and reading adcr at end of conversion reading adcr takes precedence. after adcr has been read, a new conversion result is written to adcr. <2> conflict between writing adcr and external trigger signal i nput at end of conversion the external trigger signal is not i nput during a/d conversion. therefore, the external trigger signal is not acknowledged during writing of adcr. <3> conflict between writing of adcr and writing a/d converter mode register (adm) or analog input channel specification register (ads) when adm or ads write is performed immediately a fter adcr write following t he end or a/d conversion, the conversion result is not written to t he adcr register, and intad is not generated.
chapter 11 a/d converter user?s manual u12768ej4v1ud 323 (4) countermeasures against noise to keep the resolution of 10 bits, prev ent noise from being superimposed on the av ref and ani0 to ani11 pins. the higher the output im pedance of the analog input source , the heavier the influence of noise. to lower noise, connecting an external capacitor as s hown in figure 11-6 is recommended. figure 11-6. handling of analog input pin av ref v dd v ss av dd av ss reference voltage input clamp with diode with a low v f (0.3 v max.) if noise higher than av ref or lower than av ss may be generated. c = 100 to 1000 pf (5) ani0 to ani11 the analog input (ani0 to ani11) pins function alternately as port pins. to execute a/d conversion wit h any of ani0 to ani11 selected, do not execute an instruction that inputs data to the port during conversion; otherwis e, the resolution may drop. if a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal, the expected a/d conversion result may not be obtained because of t he influence of coupling noise. therefore, do not apply a pulse to the adjacent pins. (6) input impedance of av ref pin a series resistor string is connected between the av ref and av ss pins. if the output impedance of the reference voltage source is too high, t he series resistor string between the av ref and av ss pins is connected in series, increasi ng the error of the reference voltage.
chapter 11 a/d converter user?s manual u12768ej4v1ud 324 (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the c ontents of the analog input channel specification register (ads) are changed. if the analog input pin is changed during c onversion, therefore, t he result of the a/d c onversion of the preceding analog input signal and the conversion end in terrupt request flag may be set immedi ately before ads is rewritten. if adif is read immediately after ads has been rewritten, it may be set despite the fa ct that conversion of the newly selected analog input signal has not been completed yet. when stopping a/d conversion and then resuming, clear adif before resuming conversion. figure 11-7. a/d conversion end in terrupt request generation timing remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11 rewriting ads (anin conversion starts) rewriting ads (anim conversion starts) adif is set but conversion of anim is not completed. a/d conversion adcr intad anin anin anim anim anim anin anin anim
chapter 11 a/d converter user?s manual u12768ej4v1ud 325 (8) av dd pin the av dd pin is the power supply pin of the analog circuit, and al so supplies power to the input circuit of ani0 to ani11. even in an application where a backup power supply is used, therefor e, be sure to apply the same voltage as the v dd pin to the av dd pin as shown in figure 11-8. figure 11-8. handling of av dd pin (9) reading out a/d conversion result register (adcr) a write operation to the a/d converte r mode register (adm) and analog input c hannel specification register (ads) may cause the adcr contents to be undef ined. therefore, r ead adcr during a/d conversion (adcs bit = 1). incorrect conversion results may be read out at a timing ot her than the above. av ref v dd v ss av dd av ss main power supply backup capacitor
chapter 11 a/d converter user?s manual u12768ej4v1ud 326 11.6 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identifi ed. that is, the perc entage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percent age of 1lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a per centage, and is always represented by t he following formula regardless of the resolution. 1%fsr = (max. value of analog input voltage that c an be converted ? min. value of anal og input voltage that can be converted)/100 = (av ref ? 0)/100 = av ref /100 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the ac tual measured value and t he theoretical value. zero-scale error, full-scale error, li nearity error and errors that are combi nations of these ex press the overall error. note that the quantization error is not included in the overall error in the characteristics table. figure 11-9. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0
chapter 11 a/d converter user?s manual u12768ej4v1ud 327 (3) quantization error when analog values are converted to digital values, a 1 /2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/ 2lsb is converted to the same di gital code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 11-10. quantization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 lsb) when the digita l output changes from 0??000 to 0??001. figure 11-11. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) -1 100
chapter 11 a/d converter user?s manual u12768ej4v1ud 328 (5) full-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2lsb) when the digita l output changes from 1??110 to 1??111. figure 11-12. full-scale error 100 011 010 000 0 av ref av ref ?1 av ref ?2 av ref ?3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (6) differential linearity error while the ideal width of code output is 1lsb, this indicates the differ ence between the act ual measurement value and the ideal value. figure 11-13. differential linearity error 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width
chapter 11 a/d converter user?s manual u12768ej4v1ud 329 (7) integral linearity error this shows the degree to which the c onversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement va lue and the ideal straight line when the zero-scale error and full-scale error are 0. figure 11-14. integral linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when the analog input vo ltage was applied to the time when the digital output was obtained. the sampling time is included in the conver sion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 11-15. sampling time sampling time conversion time
user?s manual u12768ej4v1ud 330 chapter 12 dma functions 12.1 functions the v850/sa1 incorporates a three c hannel dma (direct memory access) c ontroller (dmac) that controls and executes dma transfer. the dmac transfers data between inte rnal ram and on-chip peripheral i/o bas ed on a trigger from the on-chip peripheral i/o (serial interface, ti mer/counter, or a/d converter). 12.2 features { dma channels: 3 { transfer unit: 8/16 bits { maximum transfer count: 256 times (8-bit transfer) { transfer mode: single transfer { transfer clock: 4 clocks (min.) (4 f cpu ) { transfer request: request by interrupt from on-chip peripheral i/o (serial interface, timer/counter, a/d converter) { transfer target: internal ram peripheral i/o remark f cpu : cpu operation clock
chapter 12 dma functions user?s manual u12768ej4v1ud 331 12.3 configuration figure 12-1. block diagram of dmac dma transfer trigger (int signal) dma transfer request control channel controller dma peripheral i/o address register n (dioan) dma byte count register n (dbcn) dma internal ram address register n (dran) dma channel control register n (dchcn) dma transfer acknowledge signal cpu interface control internal ram internal bus intdman peripheral i/o register remark n = 0 to 2 (1) dma transfer request control block the dma transfer request control block generates a dm a transfer request signal for the cpu when the dma transfer trigger (int signal) specified by dm a channel control register n (dchcn) is input. when the dma transfer request signal is acknowledged, the cpu generates a dma transfer acknowledge signal for the channel control block and interface control bl ock after the current cpu processing has finished. (2) channel control block the channel control block distingui shes the dma transfer channel n (dma0 to dma2) to be transferred and controls the internal ram, peripheral i/o addresses, and access cycles (internal ram: 1 clock, peripheral i/o register: 3 clocks) set by the peripheral i/o registers of the channel to be transferred, the transfer direction, and the transfer count. in addition, it also controls the priority order when two or more dman transfer triggers (int signals) are generated simultaneously.
chapter 12 dma functions user?s manual u12768ej4v1ud 332 12.4 control registers (1) dma peripheral i/o address regist ers 0 to 2 (dioa0 to dioa2) these registers are used to se t the peripheral i/o register address for dma channel n. these registers are can be r ead/written in 16-bit units. after reset: undefined r/w address: dioa0 fffff180h dioa1 fffff190h dioa2 fffff1a0h 15 14 13 12 11 10 9 1 0 dioan 0 0 0 0 0 0 ioan9 to ioan1 0 (n = 0 to 2) caution the following peri pheral i/o registers must not be set in dioan. p4, p5, p6, p9, p11, p12, pm4, pm5, pm6, pm9, pm11, pm12, pmc12, mm, dwc, bcc, syc, psc, pcc, sys, prcmd, dioan, dran, dbcn, dchcn , interrupt control register (xxicn), ispr (2) dma internal ram address regi sters 0 to 2 (dra0 to dra2) these registers are used to set the internal ram address for dma channel n. an address is incremented after each transfer is completed, when the dadn bit of the dchdn register is 0. the incrementation value is ?1? during 8-bit transfers and ?2? during 16-bit transfers (n = 0 to 2). these registers are can be r ead/written in 16-bit units. after reset: undefined r/w address: dra0 fffff182h dra1 fffff192h dra2 fffff1a2h 15 14 13 12 0 dran 0 0 0 ran12 to ran0 (n = 0 to 2) caution do not set the ran12 bit to 1 in the pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 70f3015b, and 70f3015by.
chapter 12 dma functions user?s manual u12768ej4v1ud 333 the correspondence between dran setting value and internal ram area is shown below. (a) pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 70f3015b, 70f3015by set the dran register to a value in the range of 0000h to 0fffh (n = 0 to 2). setting is prohibited for values between 1000h and 1fffh. figure 12-2. correspondence between dran se tting value and internal ram (4 kb) xxffffffh xxffc000h xxffbfffh xxfff000h xxffefffh xxffe000h xxffdfffh access-prohibited area external memory area on-chip peripheral i/o area internal ram area (dran setting value) (0fffh) (0000h) 4 kb (usable for dma) cautions 1. do not set odd addresses for 16- bit transfer (dchcn register dsn = 1). 2. while the increment function is being used (dchcn register ddadn = 0), if the dran register value is set to 0fffh, it will be incremented to 1000h, and will thus become a setting-prohibited value. remark the dran register setting va lues are in the parentheses.
chapter 12 dma functions user?s manual u12768ej4v1ud 334 (b) pd703017a, 703017ay, 70f3017a, 70f3017ay set the dran register to a value in the range of 0000h to 0fffh or 1000h to 1fffh (n = 0 to 2). figure 12-3. correspondence between dran setting value and internal ram (8 kb) xxffffffh xxfff000h xxffefffh access-prohibited area external memory area on-chip peripheral i/o area internal ram area (dran setting value) (0fffh) (1000h) (1fffh) xxffc000h xxffbfffh xxffe000h xxffdfffh xxffd000h xxffcfffh (0000h) 8 kb (usable for dma) caution do not set odd addresses for 16-bit transfer (dchcn register dsn =1). remark the dran register setting va lues are in the parentheses.
chapter 12 dma functions user?s manual u12768ej4v1ud 335 (3) dma byte count registers 0 to 2 (dbc0 to dbc2) these are 8-bit registers that are used to set the number of transfers for dma channel n. the remaining number of transfers is retained during the dma transfers. a value of 1 is decremented once per tr ansfer if the transfer is a byte (8 -bit) transfer, and a value of 2 is decremented once per transfer if the tr ansfer is a 16-bit transfer. the transfers are terminated when a borrow operation occurs. accordingly, ?number of transfers ? 1? should be set for byte (8-bit) transfers and ?(number of transfers ? 1) 2? should be set for 16-bit transfers. during 16-bi t transfers, values set to bit 0 are ignored, and 0 is set to bit 0 after decrementation. these registers are can be r ead/written in 8-bit units. after reset: undefined r/w address: dbc0 fffff184h dbc1 fffff194h dbc2 fffff1a4h 7 6 5 4 3 2 1 0 dbcn bcn7 bcn6 bcn5 bcn4 bcn3 bcn2 bcn1 bcn0 (n = 0 to 2) caution values set to bit 0 are ignored during 16-bit transfers.
chapter 12 dma functions user?s manual u12768ej4v1ud 336 (4) dma channel control registers 0 to 2 (dchc0 to dchc2) these registers are used to control the dma transfer operat ion mode for dma channel n. these registers are c an be read/written in 1-bit or 8-bit units. (1/2) after reset: 00h r/w address: dchc0: fffff186h, dchc1: fffff196h, dchc2: fffff1a6h 7 6 5 4 3 2 1 0 dchcn tcn 0 dadn ttypn1 ttypn0 tdirn dsn enn (n = 0 to 2) tcn dma transfer completed/not completed note 1 0 not completed 1 completed dadn internal ram address count direction control 0 increment 1 address is fixed channel n ttypn1 ttypn0 setting of trigger for dma transfer 0 0 intcsi0/intiic0 note 2 0 1 inttm00 1 0 intad 0 1 1 inttm4 0 0 intcsi1/intsr0 0 1 intst1 1 0 intpcsi0/intiic0 note 2 1 1 1 inttm4 0 0 intsr1 0 1 intst0 1 0 intad 2 1 1 inttm5 notes 1. tcn (n = 0 to 2) is set to 1 when a specif ied number of transfers are completed, and is cleared to 0 when a write in struction is executed. 2. intiic0 is available only in the pd703014y, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay. cautions 1. dma transfer is started using an interrupt request signal (intxxn above) generated from an on-chip peripheral i/o. dma transfer is not started even if the xxifn bit of the interrupt control regist er (xxicn) that is the target of the intxxn signal is set 1. 2. if the intxxn signal is generated in synchronization with the external clock, do not set the intxxn signal as multiple dma transfer triggers at the same time. for example, do not set intcsi0 as the trigger of both dma channel 0 and dma channel 1. the trigger of the dma transfer gene rated in synchronization with the external clock is shown below. ? intcsi0 when sck0 pin input is selected as serial clock ? intcsi0 when timer 2 output (to2) that operates with ti2 pin input is selected as serial clock ? inttm4 when ti4 pin input is selected as count clock.
chapter 12 dma functions user?s manual u12768ej4v1ud 337 (2/2) tdirn transfer direction control be tween peripheral i/o and internal ram note 1 0 from internal ram to peripheral i/o 1 from peripheral i/o to internal ram dsn control of transfer data size for dma transfer note 1 0 8-bit transfer 1 16-bit transfer enn control of dma transfer enable/disable status note 2 0 disabled 1 enabled (reset to 0 after dma transfer is completed) notes 1. make sure that the transfer format conforms to the peripheral i/o register specifications (access- enabled data size, read/write, et c.) for the dma peripheral i/o address register (dioan). 2. after the specified number of transfer is completed, this bit is cleared to 0.
chapter 12 dma functions user?s manual u12768ej4v1ud 338 12.5 operation the dma controller of the v850/sa1 s upports only the single transfer mode. when a dma transfer request (intxxx: refer to 12.4 (4) dma channel control registers 0 to 2 (dchc0 to dchc2 )) is generated during cpu processing, a single dma transfe r is started after the cu rrent cpu processing has finished. regardless of the tr ansfer direction, 4 cpu clocks (f cpu ) are required for one dma transfer. the 4 cpu clocks are divided as follows. ? internal ram access: 1 clock ? peripheral i/o access: 3 clocks after one dma transfer (8/16 bits) ends, control always shi fts to the cpu processing and waits for the generation of the next dma transfer request (intxxx). after the specif ied number of data transfers ends, the dma transfer end interrupt requests (intdma0 to intdma 2) are generated for each channel of the interrupt contro ller if the tcn bit of the dochn register becomes 1. the dma transfer operation timing chart is shown below. figure 12-4. dma transfer operation timing 4 clocks t cpu dma transfer request signal processing format peripheral i/o peripheral i/o intmdan occurs when the number of transfers specified by the dbcn register end intmdan occurs when the number of transfers specified by the dbcn register end cpu processing dma transfer processing dma transfer processing access destination for transfer from internal ram to peripheral i/o 4 clocks cpu processing cpu processing ram ram peripheral i/o ram peripheral i/o ram remark n = 0 to 2 if two or more dma transfer requests are generated simu ltaneously, the dma transfer r equests are executed in a priority order of dma0 > dma1 > dma2. while a higher priority dma transfer request is being executed, the lower priority dma transfer requests are held pending. after the hi gher priority dma transfer ends, control always shifts to the cpu processing once, and then the lower priority dma transfer reques t is executed after the cpu processing ends. the processing when the transfer requests dma0 to dma2 are generated simultaneously is shown below.
chapter 12 dma functions user?s manual u12768ej4v1ud 339 figure 12-5. processing when tran sfer requests dma0 to dma2 are generated simultaneously cpu processing cpu processing dma0 processing cpu processing dma1 processing cpu processing dma2 processing transfer requests dma0 to dma2 are generated simultaneously dma operation stops only in the idle/software stop m ode. in the halt mode, dma operation continues, dma also operates during the bus hold period and after access to external memory. 12.6 cautions ? to manipulate the bits of the interr upt control register (xxicn) in the ei state when using the dma function, execute the di instruction bef ore manipulation and ei instruction after mani pulation. alternatively, clear (0) the xxifn bit at the start of the interrupt servicing routine (when not using the dma function, these manipulations are not required). ? if an interrupt request signal is generated in synchronizati on with the external clock, setting the interrupt request signal as multiple dma transfer triggers is prohibited. if set, the priority of the dma may be reversed. remark xx: peripheral unit identification name (see table 5-2 ) n: peripheral unit number (see table 5-2 )
user?s manual u12768ej4v1ud 340 chapter 13 real-time output function (rto) 13.1 function the v850/sa1 incorporates a r eal-time output function that tr ansfers preset data to real -time output buffer registers (rtbl, rtbh), and then transfers this data with hardware to an external device via the output latches, upon the occurrence of an external interrupt or external trigger. because rto can output signals wit hout jitter, it is suitable fo r controlling a stepper motor. 13.2 features { 8-bit real-time output unit { port mode and real-time output m ode can be selected in 1-bit units { 8 bits 1 channel or 4 bits 2 channels can be selected { trigger signal: selectable from the following three. external interrupt: rtptrg internal interrupt: inttm4, inttm5
chapter 13 real-time output function (rto) user?s manual u12768ej4v1ud 341 13.3 configuration figure 13-1. block diagram of rto output latch rtp7 real-time output port mode register (rtpm) real-time output buffer register, higher 4 bits (rtbh) output trigger controller 4 rtpoe rtpeg byte extr rtptrg real-time output port control register (rtpc) internal bus real-time output buffer register, lower 4 bits (rtbl) inttm4 inttm5 rtp6 rtp5 rtp4 rtp3 rtp2 rtp1 rtp0 rto consists of the following hardware. table 13-1. configuration of rto item configuration registers real-time output bu ffer registers (rtbl, rtbh) control registers real-time output port mode register (rtpm) real-time output port control register (rtpc)
chapter 13 real-time output function (rto) user?s manual u12768ej4v1ud 342 (1) real-time output buffer registers (rtbl, rtbh) rtbl and rtbh are 4-bit registers that hold output data in advance. these registers are mapped to independent addresses in the special functi on register (sfr) area as shown in figure 13-2. if an operation mode of 4 bits 2 channels is specified, dat a can be individually set to rtbl and rtbh. the data of both the registers can be read all at once by specifying the addr ess of either of the registers. if an operation mode of 8 bits 1 channel is specified, 8- bit data can be set to both rtbl and rtbh respectively by writing the data to either of the registers. the dat a of both the registers can be read all at once by specifying the address of either of the registers. these registers are set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 13-2 shows the configurati on of rtbl and rtbh, and table 13-2 shows the operation to be performed when rtbl and rtbh are manipulated. figure 13-2. configuration of r eal-time output buffer registers higher 4 bits lower 4 bits rtbl rtbh table 13-2. operation when real-time output buffer registers are manipulated read note 1 write note 2 operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl rtbh rtbl invalid rtbl 4 bits 2 channels rtbh rtbh rtbl rtbh invalid rtbl rtbh rtbl rtbh rtbl 8 bits 1 channel rtbh rtbh rtbl rtbh rtbl notes 1. only the bits set in the real-t ime output port mode (rtpm) can be read. if a bit set in the port mode is read, 0 is read. 2. set output data to rtbl and rtbh after setting t he real-time output port unt il the real-time output trigger is generated. (2) output latch this is the output latch to which the value set by the real-time output buffer r egister (rtbl, rtbh) is automatically transferred when the r eal-time output trigger occurs. ou tput latches cannot be accessed. a port specified as a real-tim e output port cannot set data to the port output latch. to se t the initial values of the real-time output port, set data to the port output latch in the port mode and t hen set to the real-time output port mode (refer to 13.5 usage ).
chapter 13 real-time output function (rto) user?s manual u12768ej4v1ud 343 13.4 control registers rto is controlled by using the following two registers. real-time output port mode register (rtpm) real-time output port cont rol register (rtpc) (1) real-time output port mode register (rtpm) this register selects real-time output port mode or port mode in 1-bit units. rtpm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets rtpm to 00h. after reset: 00h r/w address: fffff3a4h 7 6 5 4 3 2 1 0 rtpm rtpm7 rtpm6 rtpm5 rtpm 4 rtpm3 rtpm2 rtpm1 rtpm0 rtpmn selection of real-time output port (n = 0 to 7) 0 port mode 1 real-time output port mode cautions 1. set a port pin to the output mode wh en it is used as a real-time output port pin. 2. data cannot be set to the output latch for a port pin set as a real-time output port pin. to set an initial value, therefore, set the data to the output latch before setting the port pin to the real-time output port mode (refer to 13.5 usage).
chapter 13 real-time output function (rto) user?s manual u12768ej4v1ud 344 (2) real-time output port control register (rtpc) this register sets the operation mode and out put trigger of the r eal-time output port. the relationship between the operation m ode and output trigger of t he real-time output port is as shown in table 13- 3. rtpc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets rtpc to 00h. after reset: 00h r/w address: fffff3a6h 7 6 5 4 3 2 1 0 rtpc rtpoe rtpeg byte extr 0 0 0 0 rtpoe control of operation of real-time output port 0 operation disabled note 1 operation enabled rtpeg valid edge of rtptrg signal 0 falling edge 1 rising edge byte operation mode of real-time output port 0 4 bits 2 channels 1 8 bits 1 channel extr control of real-time output by rtptrg signal 0 rtptrg not used as r eal-time output trigger 1 rtptrg used as real -time output trigger note rtp0 to rtp7 output 0 if the real-tim e output operation is disabled (rtpoe = 0). table 13-3. operation mode and output trigger of real-time output port byte extr operation mode rtbh port output rtbl port output 0 0 4 bits 2 channels inttm5 inttm4 1 inttm4 rtptrg 1 0 8 bits 1 channel inttm4 1 rtptrg
chapter 13 real-time output function (rto) user?s manual u12768ej4v1ud 345 13.5 usage (1) disable the real-t ime output operation. clear bit 7 (rtpoe) of the real-time output port control register (rtpc) to 0. (2) initialization (i) set the initial value to the output latch of port 10. (ii) set the pm10 regi ster to output mode. (iii) specify the real-t ime output port mode or port mode in 1-bit units. set the real-time output port mode register (rtpm). (iv) selects a trigger and valid edge. set bits 4, 5, and 6 (ext r, byte, and rtpeg) of rtpc. (v) set the same value as (i) to the real -time output buffer regi sters (rtbh and rtbl). (3) enable the real-t ime output operation. set rtpoe to 1. (4) set the output latch of port 10 to 0 are set the next out put to rtbh and rtbl before the selected transfer trigger is generated. (5) set the next real-time output value to rtbh and rtbl by interrupt servic ing corresponding to the selected trigger.
chapter 13 real-time output function (rto) user?s manual u12768ej4v1ud 346 13.6 operation if the real-time output operati on is enabled by setting bit 7 (rtpoe) of t he real-time output por t control register (rtpc) to 1, the data of t he real-time output buffer registers (rtbh and rt bl) is transferred to the output latch in synchronization with the generati on of the selected transfer tr igger (set by extr and byte note ). of the transferred data, only the data of the bits specified in the real-time output port mode by the real-t ime output port mode register (rtpm) is output from the bits of rtp0 to rtp7. t he bits specified in the por t mode by rtpm output 0. if the real-time output operati on is disabled by clearing rtpoe to 0, rt p0 to rtp7 output 0 regardless of the setting of rtpm. note extr: bit 4 of real-time output port control register (rtpc) byte: bit 5 of real-time output port control register (rtpc) figure 13-3. example of operation timing of rto (when extr = 0, byte = 0) inttm5 (internal) inttm4 (internal) cpu operation rtbh rtbl rt output latch (h) rt output latch (l) a b a b a b a b d01 d02 d03 d04 d11 d12 d13 d14 d01 d02 d03 d04 d11 d12 d13 d14 a: software processing by interrupt request input to inttm5 (rtbh write) b: software processing by interrupt request input to inttm4 (rtbl write)
chapter 13 real-time output function (rto) user?s manual u12768ej4v1ud 347 13.7 cautions (1) before performing initialization, dis able the real-time output oper ation by clearing bit 7 (rtpoe) of the real-time output port control register (rtpc) to 0. (2) once the real-time output operation is disabled (rtpoe = 0), be sure to set the same initial value as the output latch to the real-time output buffe r registers (rtbh and rtbl) before enab ling the real-tim e output operation (rtpoe = 0 1). (3) operation cannot be guarant eed if a conflict between the following signal s occurs. use a software to avoid a conflict. ? conflict between the switch operati on from the real-time output port m ode to the port mode (rtpoe = 0) and the valid edge of the selected real-time output trigger ? conflict between the write operation to the real-time output buffer register (rtbl, rtbh) in the real-time output port mode and the valid edge of the se lected real-time output trigger
user?s manual u12768ej4v1ud 348 chapter 14 port function 14.1 port configuration the v850/sa1 includes 85 i/o port pins configuri ng ports 0 to 12 (13 ports are input only). there are three power supplies for the i/o buffers; av dd , bv dd , and v dd , which are described below. table 14-1. pin i/o buffer power supplies power supply corresponding pins usable voltage range av dd port 7, port 8 2.7 v av dd 3.6 v bv dd port 4, port 5, port 6, port 9, port 12 clkout 2.7 v bv dd 3.6 v v dd port 0, port 1, port 2, port 3, port 10, port 11, reset 2.7 v v dd 3.6 v 14.2 port pin function 14.2.1 port 0 port 0 is an 8-bit i/o port for which i/o settings can be cont rolled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). when p00 to p04 are used as the nmi and intp0 to intp3 pins, noise is eliminated fr om these pins by an analog noise eliminator. when p05 to p07 are used as the intp4/adtrg, intp5/rt ptrg, and intp6 pins, noise is eliminated from these pins by a digital noise eliminator. after reset: 00h r/w address: fffff000h 7 6 5 4 3 2 1 0 p0 p07 p06 p05 p04 p03 p02 p01 p00 p0n control of output data (in output mode) (n = 0 to 7) 0 output 0 1 output 1 remark in input mode: when port 0 (p0) is read, the pin le vels at that time are read. writing to p0 writes the values to that register. this does not affect the input pins. in output mode: when port 0 (p0) is read, the p0 values are read. writing to p0 writes the values to that register , and those values are immediately output.
chapter 14 port function user?s manual u12768ej4v1ud 349 port 0 includes the following alternate functions. table 14-2. alternate functions of port 0 pin name alternate function i/o pull note remark p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 analog noise elimination p05 intp4/adtrg p06 intp5/rtptrg port 0 p07 intp6 i/o yes digital noise elimination note software pull-up function (1) function of p0 pins port 0 is an 8-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 0 mode register (pm0). in output mode, the values set to each bit are output to port 0 (p0). when us ing this port in output mode, either the valid edge of each interrupt r equest should be made invalid or each interrupt request should be masked (except for nmi requests). when using this port in input mode, t he pin statuses can be read by reading p0 . also, the p0 register (output latch) values can be read by r eading p0 while in output mode. the valid edge of nmi and intp0 to intp6 are specified vi a rising edge specification r egister 0 (egp0) and falling edge specification register 0 (egn0). a pull-up resistor can be connected in 1-bit units when s pecified via pull-up resistor option register 0 (pu0). when a reset is input, the settings are initialized to i nput mode. also, the valid edge of each interrupt request becomes invalid (nmi and intp0 to intp6 do not function immediately after reset). (2) noise elimination (a) elimination of noise from nmi and intp0 to intp3 pins an on-chip noise eliminator uses analog delay to elim inate noise. consequently, if a signal having a constant level is input for longer than a specif ied time to these pins, it is detec ted as a valid edge. such edge detection occurs after the specified amount of time. (b) elimination of noise from intp4 to intp6, adtrg, and rtptrg pins a digital noise eliminator is provided on chip. this circuit uses digital sampling. a pin?s input level is detected using a sampling clock (f xx ), and noise elimination is performed if the same level is not detected three times consecutively.
chapter 14 port function user?s manual u12768ej4v1ud 350 cautions 1. if the input pulse width is 2 to 3 clo cks, whether it will be detected as a valid edge or eliminated as noise is undefined. 2. to ensure correct detection of pulses as va lid edges, constant-l evel input is required for 3 clocks or more. 3. if noise is occurring in synchronizati on with the sampling clock, noise cannot be eliminated. in such cases, attach a filter to the input pins to eliminate the noise. 4. noise elimination is not performed when these pins are used as an normal input port pins. (3) control registers (a) port 0 mode register (pm0) pm0 can be read/written in 1-bit or 8-bit units. after reset: ffh r/w address: fffff020h 7 6 5 4 3 2 1 0 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) pull-up resistor option register 0 (pu0) pu0 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff080h 7 6 5 4 3 2 1 0 pu0 pu07 pu06 pu05 pu04 pu03 pu02 pu01 pu00 pu0n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect
chapter 14 port function user?s manual u12768ej4v1ud 351 (c) rising edge specification register 0 (egp0) egp0 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff0c0h 7 6 5 4 3 2 1 0 egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n control of rising edge detection (n = 0 to 7) 0 interrupt request signal di d not occur at rising edge 1 interrupt request signal occurred at rising edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins (d) falling edge specification register 0 (egn0) egn0 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff0c2h 7 6 5 4 3 2 1 0 egn0 egn07 egn06 egn05 egn04 egn03 egn02 egn01 egn00 egn0n control of falling edge detection (n = 0 to 7) 0 interrupt request signal did not occur at falling edge 1 interrupt request signal occurred at falling edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins
chapter 14 port function user?s manual u12768ej4v1ud 352 (4) block diagram (port 0) figure 14-1. block di agram of p00 to p07 remarks 1. pu0: pull-up resistor option register 0 pm0: port 0 mode register rd: read signal of port 0 wr: write signal of port 0 2. n = 0 to 7 wr pu pu0n pm0n pu0 v dd p-ch p00/nmi p01/intp0 p02/intp1 p03/intp2 p04/intp3 p05/intp4/adtrg p06/intp5/rtptrg p07/intp6 pm0 rd wr port wr pm output latch (p0n) internal bus alternate function selector
chapter 14 port function user?s manual u12768ej4v1ud 353 14.2.2 port 1 port 1 is a 6-bit i/o port for which i/o settings can be cont rolled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). bits 0, 1, 2, 4, and 5 are selectable as normal outputs or n- ch open-drain outputs. after reset: 00h r/w address: fffff002h 7 6 5 4 3 2 1 0 p1 0 0 p15 p14 p13 p12 p11 p10 p1n control of output data (in output mode) (n = 0 to 5) 0 output 0 1 output 1 remark in input mode: when port 1 (p1) is read, the pin le vels at that time are read. writing to p1 writes the values to that register. this does not affect the input pins. in output mode: when port 1 (p1) is read, t he p1 values are read. writing to p1 writes the values to that register, and those values are immediately output. port 1 includes the following alternate functions. table 14-3. alternate functions of port 1 pin name alternate function i/o pull note 1 remark port 1 p10 si0/sda note 2 i/o yes selectable as n-ch open-drain output p11 so0 p12 sck0/scl0 note 2 p13 si1/rxd0 ? p14 so1/txd0 selectable as n-ch open-drain output p15 sck1/asck0 notes 1. software pull-up function 2. pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, 70f3017ay only.
chapter 14 port function user?s manual u12768ej4v1ud 354 (1) function of p1 pins port 1 is a 6-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 1 mode register (pm1). in output mode, the values set to eac h bit are output to port 1 (p1). the por t 1 function register (pf1) can be used to specify whether p10 to p12, p14, and p 15 are normal outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading p1. also, the p1 (output latch) values can be read by reading p1 while in output mode. a pull-up resistor can be connected in 1-bit units when s pecified via pull-up resistor option register 1 (pu1). clear p1 and pm1 to 0 when using alter nate-function pins as out puts. the ored result of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 1 mode register (pm1) pm1 can be read/written in 1-bit or 8-bit units. after reset: 3fh r/w address: fffff022h 7 6 5 4 3 2 1 0 pm1 0 0 pm15 pm14 pm13 pm12 pm11 pm10 pm1n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode
chapter 14 port function user?s manual u12768ej4v1ud 355 (b) pull-up resistor option register 1 (pu1) pu1 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff082h 7 6 5 4 3 2 1 0 pu1 0 0 pu15 pu14 pu13 pu12 pu11 pu10 pu1n control of on-chip pull-up resistor connection (n = 0 to 5) 0 do not connect 1 connect (c) port 1 function register (pf1) pf1 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff0a2h 7 6 5 4 3 2 1 0 pf1 0 0 pf15 pf14 0 note pf12 pf11 pf10 pf1n control of normal output/n-ch open-drain output (n = 0 to 2, 4, 5) 0 normal output 1 n-ch open-drain output note bit 3 is fixed to normal output.
chapter 14 port function user?s manual u12768ej4v1ud 356 (3) block diagrams (port 1) figure 14-2. block diagra m of p10, p12, and p15 note available only in the pd703014ay, 703014by, 703015ay, 703015 by, 703017ay, 70f3015by, and 70f3017ay remarks 1. pu1: pull-up resistor option register 1 pf1: port 1 function register pm1: port 1 mode register rd: read signal of port 1 wr: write signal of port 1 2. n = 0, 2, 5 wr pu wr pf wr port wr pm rd pu1n pu1 pf1n pf1 pm1n pm1 p-ch p-ch n-ch p10/si0/sda note p12/sck0/scl note p15/sck1/asck0 v dd v dd output latch (p1n) internal bus alternate function alternate function selector
chapter 14 port function user?s manual u12768ej4v1ud 357 figure 14-3. block diagram of p11 and p14 remarks 1. pu1: pull-up resistor option register 1 pf1: port 1 function register pm1: port 1 mode register rd: read signal of port 1 wr: write signal of port 1 2. n = 1, 4 wr pu wr pf wr port wr pm rd pu1n pu1 pf1n pf1 pm1n pm1 p-ch p-ch n-ch p11/so0 p14/so1/txd0 v dd v dd alternate function internal bus selector output latch (p1n)
chapter 14 port function user?s manual u12768ej4v1ud 358 figure 14-4. block diagram of p13 remark pu1: pull-up resistor option register 1 pm1: port 1 mode register rd: read signal of port 1 wr: write signal of port 1 wr pu pu13 pm13 pu1 v dd p-ch p13/si1/rxd0 pm1 rd wr port wr pm output latch (p13) internal bus alternate function selector
chapter 14 port function user?s manual u12768ej4v1ud 359 14.2.3 port 2 port 2 is an 8-bit i/o port for which i/o settings can be cont rolled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). p21 and p22 are selectable as normal outputs or n-ch open-drain outputs. when p26 and p27 are used as the ti2/ti3 pins, noise is eliminated from t hese pins by a digital noise eliminator. after reset: 00h r/w address: fffff004h 7 6 5 4 3 2 1 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 p2n control of output data (in output mode) (n = 0 to 7) 0 output 0 1 output 1 remark in input mode: when port 2 (p2) is read, the pin levels at that time are read. writing to p2 writes the values to that register. this does not affect the input pins. in output mode: when port 2 (p2) is read, the p2 values are read. writing to p2 writes the values to that register , and those values are immediately output. port 2 includes the following alternate functions. table 14-4. alternate functions of port 2 pin name alternate function i/o pull note remark port 2 p20 si2 ? p21 so2 selectable as n-ch open-drain output p22 sck2 p23 rxd1 ? p24 txd1 p25 asck1 p26 ti2/to2 p27 ti3/to3 i/o yes digital noise elimination note software pull-up function
chapter 14 port function user?s manual u12768ej4v1ud 360 (1) function of p2 pins port 2 is an 8-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 2 mode register (pm2). in output mode, the values set to eac h bit are output to port 2 (p2). the por t 2 function register (pf2) can be used to specify whether p21 and p22 are norma l outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading p2. also, the p2 (output latch) values can be read by reading p2 while in output mode. a pull-up resistor can be connected in 1-bit units when s pecified via pull-up resistor option register 2 (pu2). when using the alternate function ti2 and ti3 pins, noise elimination is prov ided by a digital noise eliminator (same as digital noise eliminator for port 0). clear p2 and pm2 to 0 when using alter nate-function pins as out puts. the ored result of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 2 mode register (pm2) pm2 can be read/written in 1-bit or 8-bit units. after reset: ffh r/w address: fffff024h 7 6 5 4 3 2 1 0 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode
chapter 14 port function user?s manual u12768ej4v1ud 361 (b) pull-up resistor option register 2 (pu2) pu2 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff084h 7 6 5 4 3 2 1 0 pu2 pu27 pu26 pu25 pu24 pu23 pu22 pu21 pu20 pu2n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect (c) port 2 function register (pf2) pf2 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff0a4h 7 6 5 4 3 2 1 0 pf2 0 0 0 0 0 pf22 pf21 0 pf2n control of normal output/n-ch open-drain output (n = 1, 2) 0 normal output 1 n-ch open-drain output
chapter 14 port function user?s manual u12768ej4v1ud 362 (3) block diagrams (port 2) figure 14-5. block diagra m of p20, p23, and p25 remarks 1. pu2: pull-up resistor option register 2 pm2: port 2 mode register rd: read signal of port 2 wr: write signal of port 2 2. n = 0, 3, 5 wr pu pu2n pm2n selector output latch (p2n) alternate function internal bus pu2 v dd p-ch p20/si2 p23/rxd1 p25/asck1 pm2 rd wr port wr pm
chapter 14 port function user?s manual u12768ej4v1ud 363 figure 14-6. block diagram of p21 remark pu2: pull-up resistor option register 2 pf2: port 2 function register pm2: port 2 mode register rd: read signal of port 2 wr: write signal of port 2 wr pu wr pf wr port wr pm rd pu21 pu2 pf21 pf2 pm21 selector output latch (p21) alternate function pm2 internal bus p-ch p-ch n-ch p21/so2 v dd v dd
chapter 14 port function user?s manual u12768ej4v1ud 364 figure 14-7. block diagram of p22 remark pu2: pull-up resistor option register 2 pf2: port 2 function register pm2: port 2 mode register rd: read signal of port 2 wr: write signal of port 2 wr pu wr pf wr port wr pm rd pu22 pu2 pf22 pf2 pm22 selector output latch (p22) pm2 alternate function alternate function internal bus p-ch p-ch n-ch p22/sck2 v dd v dd
chapter 14 port function user?s manual u12768ej4v1ud 365 figure 14-8. block diagram of p24 remark pu2: pull-up resistor option register 2 pm2: port 2 mode register rd: read signal of port 2 wr: write signal of port 2 wr pu pu24 pm24 internal bus pu2 v dd p-ch p24/txd1 pm2 selector alternate function output latch (p24) rd wr port wr pm
chapter 14 port function user?s manual u12768ej4v1ud 366 figure 14-9. block diagram of p26 and p27 remarks 1. pu2: pull-up resistor option register 2 pm2: port 2 mode register rd: read signal of port 2 wr: write signal of port 2 2. n = 6, 7 wr pu pu2n pm2n pu2 v dd p-ch p26/ti2/to2 p27/ti3/to3 pm2 alternate function alternate function selector output latch (p2n) internal bus rd wr port wr pm
chapter 14 port function user?s manual u12768ej4v1ud 367 14.2.4 port 3 port 3 is an 8-bit i/o port for which i/o settings can be cont rolled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). when p36 and p37 are used as the ti4 and ti5 pins, noise is eliminated from these pins by a digital noise eliminator. after reset: 00h r/w address: fffff006h 7 6 5 4 3 2 1 0 p3 p37 p36 p35 p34 p33 p32 p31 p30 p3n control of output data (in output mode) (n = 0 to 7) 0 output 0 1 output 1 remark in input mode: when port 3 (p3) is read, the pin levels at that ti me are read. writing to p3 writes the values to that register. this does not affect the input pins. in output mode: when port 3 (p3) is read, t he p3 values are read. writing to p3 writes the values to that register, and those values are immediately output. port 3 includes the following alternate functions. table 14-5. alternate functions of port 3 pin name alternate function i/o pull note remark p30 ti00 p31 ti01 p32 ti10 p33 ti11 p34 to0/a13 p35 to1/a14 ? p36 ti4/to4/a15 port 3 p37 ti5/to5 i/o yes digital noise elimination note software pull-up function
chapter 14 port function user?s manual u12768ej4v1ud 368 (1) function of p3 pins port 3 is an 8-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 3 mode register (pm3). in output mode, the values set to each bit are output to port 3 (p3). when using this port in input mode, the pin statuses can be read by reading p3. also, the p3 (output latch) values can be read by reading p3 while in output mode. a pull-up resistor can be connected in 1-bit units when s pecified via pull-up resistor option register 3 (pu3). when using the alternate-func tion ti4 and ti5 pins, noise elimination is provided by a digital noise eliminator (same as digital noise eliminator for port 0). when using the alternate-function a13 to a15 pins, se t the pin functions via t he memory address output mode register (mam). at this time, be sure to set pm3 (pm34 to pm36) to 0. clear p3 and pm3 to 0 when using alter nate-function pins as out puts. the ored result of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 3 mode register (pm3) pm3 can be read/written in 1-bit or 8-bit units. after reset: ffh r/w address: fffff026h 7 6 5 4 3 2 1 0 pm3 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) pull-up resistor option register 3 (pu3) pu3 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff086h 7 6 5 4 3 2 1 0 pu3 pu37 pu36 pu35 pu34 pu33 pu32 pu31 pu30 pu3n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect
chapter 14 port function user?s manual u12768ej4v1ud 369 (3) block diagrams (port 3) figure 14-10. block di agram of p30 to p33 remarks 1. pu3: pull-up resistor option register 3 pm3: port 3 mode register rd: read signal of port 3 wr: write signal of port 3 2. n = 0 to 3 wr pu pu3n pm3n pu3 output latch (p3n) internal bus v dd p-ch p30/ti00 p31/ti01 p32/ti10 p33/ti11 pm3 rd selector alternate function wr port wr pm
chapter 14 port function user?s manual u12768ej4v1ud 370 figure 14-11. block diagram of p34 and p35 remarks 1. pu3: pull-up resistor option register 3 pm3: port 3 mode register rd: read signal of port 3 wr: write signal of port 3 2. n = 4, 5 wr pu pu3n pm3n pu3 selector alternate function output latch (p3n) internal bus v dd p-ch p34/to0/a13 p35/to1/a14 pm3 rd wr port wr pm
chapter 14 port function user?s manual u12768ej4v1ud 371 figure 14-12. block diagram of p36 and p37 remarks 1. pu3: pull-up resistor option register 3 pm3: port 3 mode register rd: read signal of port 3 wr: write signal of port 3 2. n = 6, 7 wr pu pu3n selector output latch (p3n) pm3n pu3 v dd p-ch p36/ti4/to4/a15 p37/ti5/to5 pm3 alternate function alternate function internal bus rd wr port wr pm
chapter 14 port function user?s manual u12768ej4v1ud 372 14.2.5 ports 4 and 5 ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff008h, fffff00ah 7 6 5 4 3 2 1 0 pn pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 (n = 4, 5) pnx control of output data (in output mode) (n = 4, 5, x = 0 to 7) 0 output 0 1 output 1 remark in input mode: when port 4 (p4) and port 5 (p5) ar e read, the pin levels at that time are read. writing to p4 and p5 writes the values to those registers. this does not affect the input pins. in output mode: when port 4 (p4) and port 5 (p5) are read, their val ues are read. writing to p4 and p5 writes the values to those register s, and those values are immediately output. ports 4 and 5 include the following alternate functions. table 14-6. alternate functions of ports 4 and 5 pin name alternate function i/o pull note remark port 4 p40 ad0 i/o no ? p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 ad7 port 5 p50 ad8 i/o no ? p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 ad15 note software pull-up function
chapter 14 port function user?s manual u12768ej4v1ud 373 (1) functions of p4 and p5 pins ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 4 mode register (pm4 ) and port 5 mode register (pm5). in output mode, the values set to each bi t are output to ports 4 and 5 (p4 and p5). when using these ports in input mode, the pin statuses can be read by r eading p4 and p5. also, the p4 and p5 (output latch) values can be read by reading p4 and p5 while in output mode. a software pull-up function is not implemented. when using the alternate-function ad0 to ad15 pins, set the pin functions via the memory expansion mode register (mm). this does not affect pm4 and pm5. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 4 mode register and port 5 mode register (pm4 and pm5) pm4 and pm5 can be read/written in 1-bit or 8-bit units. after reset: ff h r/w address: fffff028h, fffff02ah 7 6 5 4 3 2 1 0 pmn pmn7 pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 (n = 4, 5) pmnx control of i/o mode (n = 4, 5, x = 0 to 7) 0 output mode 1 input mode
chapter 14 port function user?s manual u12768ej4v1ud 374 (3) block diagram (port 4, port 5) figure 14-13. block diagram of p40 to p47 and p50 to p57 rd wr port wr pm wr mm pmmn pmm mm i/o controller selector selector alternate function alternate function output latch (pmn) internal bus pmn/ad x remarks 1. pm4: port 4 mode register pm5: port 5 mode register mm: memory expansion mode register rd: read signals of ports 4 and 5 wr: write signals of ports 4 and 5 2. m = 4, 5 n = 0 to 7 x = 0 to 15
chapter 14 port function user?s manual u12768ej4v1ud 375 14.2.6 port 6 port 6 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff00ch 7 6 5 4 3 2 1 0 p6 0 0 p65 p64 p63 p62 p61 p60 p6n control of output data (in output mode) (n = 0 to 5) 0 output 0 1 output 1 remark in input mode: when port 6 (p6) is read, the pin levels at that time are read. writing to p6 writes the values to that register. this does not affect the input pins. in output mode: when port 6 (p6) is read, t he p6 values are read. writing to p6 writes the values to that register, and those values are immediately output. port 6 includes the following alternate functions. table 14-7. alternate functions of port 6 pin name alternate function i/o pull note remark port 6 p60 a16 i/o no ? p61 a17 p62 a18 p63 a19 p64 a20 p65 a21 note software pull-up function (1) function of p6 pins port 6 is a 6-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 6 mode register (pm6). in output mode, the values set to each bit are output to port 6 (p6). when using this port in input mode, the pin statuses can be read by reading p6. also, the p6 (output latch) values can be read by reading p6 while in output mode. a software pull-up functi on is not implemented. when using the alternate-function a16 to a21 pins, set t he pin functions via the memo ry expansion mode register (mm). this does not affect pm6. when a reset is input, the settings are initialized to input mode.
chapter 14 port function user?s manual u12768ej4v1ud 376 (2) control register (a) port 6 mode register (pm6) pm6 can be read/written in 1-bit or 8-bit units. after reset: 3fh r/w address: fffff02ch 7 6 5 4 3 2 1 0 pm6 0 0 pm65 pm64 pm63 pm62 pm61 pm60 pm6n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode (3) block diagram (port 6) figure 14-14. block di agram of p60 to p65 rd output latch (p6n) internal bus wr port wr pm wr mm pm6n mm pm6 i/o controller selector selector alternate function p6n/a x remarks 1. pm6: port 6 mode register mm: memory expansion mode register rd: read signal of port 6 wr: write signal of port 6 2. n = 0 to 5 x = 16 to 21
chapter 14 port function user?s manual u12768ej4v1ud 377 14.2.7 ports 7 and 8 port 7 is an 8-bit input-only port and port 8 is a 4-bit input -only port. both ports are read-only and are accessible in 8-bit or 1-bit units. after reset: undefined r address: fffff00eh 7 6 5 4 3 2 1 0 p7 p77 p76 p75 p74 p73 p72 p71 p70 p7n pin level (n = 0 to 7) 0/1 read pin level of bit n after reset: undefined r address: fffff010h 7 6 5 4 3 2 1 0 p8 0 0 0 0 p83 p82 p81 p80 p8n pin level (n = 0 to 3) 0/1 read pin level of bit n ports 7 and 8 include the following alternate functions. table 14-8. alternate functions of ports 7 and 8 pin name alternate function i/o pull note remark port 7 p70 ani0 input no ? p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 ani7 port 8 p80 ani8 input no ? p81 ani9 p82 ani10 p83 ani11 note software pull-up function
chapter 14 port function user?s manual u12768ej4v1ud 378 (1) functions of p7 and p8 pins port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. the pin statuses can be read by r eading ports 7 and 8 (p7 and p8). data cannot be written to p7 or p8. a software pull-up function is not implemented. values read from pins specified as analog inputs are undefined values. do not read values from p7 or p8 during a/d conversion. (2) block diagram (port 7, port 8) figure 14-15. block diagram of p70 to p77 and p80 to p83 rd selector selector alternate function internal bus wr port wr pm wr mm pm9n i/o controller output latch (p9n) mm pm9 p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak remarks 1. rd: read signals of ports 7 and 8 2. m = 7, 8 n = 0 to 7 (when m = 7), 0 to 3 (when m = 8) x = 0 to 7 (when m = 7), 8 to 11 (when m = 8)
chapter 14 port function user?s manual u12768ej4v1ud 379 14.2.8 port 9 port 9 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff012h 7 6 5 4 3 2 1 0 p9 0 p96 p95 p94 p93 p92 p91 p90 p9n control of output data (in output mode) (n = 0 to 6) 0 output 0 1 output 1 remark in input mode: when port 9 (p9) is read, the pin levels at that ti me are read. writing to p9 writes the values to that register. this does not affect the input pins. in output mode: when port 9 (p9) is read, t he p9 values are read. writing to p9 writes the values to that register, and those values are immediately output. port 9 includes the following alternate functions. table 14-9. alternate functions of port 9 pin name alternate function i/o pull note remark p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak port 9 p96 hldrq i/o no ? note software pull-up function
chapter 14 port function user?s manual u12768ej4v1ud 380 (1) function of p9 pins port 9 is a 7-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 9 mode register (pm9). in output mode, the values set to each bit are output to port 9 (p9). when using this port in input mode, the pin statuses can be read by reading p9. also, the p9 (output latch) values can be read by reading p9 while in output mode. a software pull-up functi on is not implemented. when using the alternate-function ex ternal expansion function pins, set the pin functions via the memory expansion mode register (mm). when a reset is input, the settings are initialized to input mode. caution when using port 9 as an i/o port, set the bic bit of the system control register (syc) to 0. after the system is reset, the bic bit is 0. (2) control register (a) port 9 mode register (pm9) pm9 can be read/written in 1-bit or 8-bit units. after reset: 7fh r/w address: fffff032h 7 6 5 4 3 2 1 0 pm9 0 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n control of i/o mode (n = 0 to 6) 0 output mode 1 input mode
chapter 14 port function user?s manual u12768ej4v1ud 381 (3) block diagrams (port 9) figure 14-16. block di agram of p90 to p95 rd selector selector alternate function internal bus wr port wr pm wr mm pm9n i/o controller output latch (p9n) mm pm9 p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak remarks 1. pm9: port 9 mode register mm: memory expansion mode register rd: read signal of port 9 wr: write signal of port 9 2. n = 0 to 5
chapter 14 port function user?s manual u12768ej4v1ud 382 figure 14-17. block diagram of p96 rd selector alternate function i/o controller output latch (p96) internal bus wr port wr pm wr mm pm96 mm pm9 p96/hldrq remark pm9: port 9 mode register mm: memory expansion mode register rd: read signal of port 9 wr: write signal of port 9
chapter 14 port function user?s manual u12768ej4v1ud 383 14.2.9 port 10 port 10 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). the pins in this port are selectable as normal outputs or n- ch open-drain outputs. after reset: 00h r/w address: fffff014h 7 6 5 4 3 2 1 0 p10 p107 p106 p105 p104 p103 p102 p101 p100 p10n control of output data (in output mode) (n = 0 to 7) 0 output 0 1 output 1 remark in input mode: when port 10 (p10) is read, the pin le vels at that time are read. writing to p10 writes the values to that register. this does not affect the input pins. in output mode: when port 10 (p10) is read, the p10 values are read. writing to p10 writes the values to that register, and those values are immediately output. port 10 includes the following alternate functions. table 14-10. alternate functions of port 10 pin name alternate function i/o pull note remark port 10 p100 rtp0/a5 i/o yes selectable as n-ch open-drain outputs p101 rtp1/a6 p102 rtp2/a7 p103 rtp3/a8 p104 rtp4/a9 p105 rtp5/a10 p106 rtp6/a11 p107 rtp7/a12 note software pull-up function
chapter 14 port function user?s manual u12768ej4v1ud 384 (1) function of p10 pins port 10 is an 8-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 10 mode register (pm10). in output mode, the values set to eac h bit are output to port 10 (p10). the por t 10 function register (pf10) can be used to specify whether outputs are norma l outputs or n-ch open-drain outputs. when using this port in input mode, t he pin statuses can be read by reading p 10. also, the p10 (output latch) values can be read by reading p10 while in output mode. a pull-up resistor can be connected in 1-bit units when s pecified via pull-up resistor option register 10 (pu10). when using the alternate-function a5 to a12 pins, se t the pin functions via t he memory address output mode register (mam). at this time , be sure to set pm10 to 0. when using alternate-function pins as outputs, the ored result of the port output and the al ternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. caution when using port 10 as a real-time output port, set in accordance with 13. 5 usage. (2) control registers (a) port 10 mode register (pm10) pm10 can be read/written in 1-bit or 8-bit units. after reset: ffh r/w address: fffff034h 7 6 5 4 3 2 1 0 pm10 pm107 pm106 pm105 pm104 pm103 pm102 pm101 pm100 pm10n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode
chapter 14 port function user?s manual u12768ej4v1ud 385 (b) pull-up resistor option register 10 (pu10) pu10 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff094h 7 6 5 4 3 2 1 0 pu10 pu107 pu106 pu105 pu104 pu103 pu102 pu101 pu100 pu10n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect (c) port 10 function register (pf10) pf10 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff0b4h 7 6 5 4 3 2 1 0 pf10 pf107 pf106 pf105 pf104 pf103 pf102 pf101 pf100 pf10n control of normal output/n-ch open-drain output (n = 0 to 7) 0 normal output 1 n-ch open-drain output
chapter 14 port function user?s manual u12768ej4v1ud 386 (3) block diagram (port 10) figure 14-18. block di agram of p100 to p107 remarks 1. pu10: pull-up resistor option register 10 pf10: port 10 function register pm10: port 10 mode register rd: read signal of port 10 wr: write signal of port 10 2. n = 0 to 7 x = 5 to 12 wr pu wr pf wr port wr pm rd alternate function pu10n pu10 output latch (p10n) selector internal bus pf10n pf10 pm10n pm10 p-ch p-ch n-ch p10n/rtpn/a x v dd v dd
chapter 14 port function user?s manual u12768ej4v1ud 387 14.2.10 port 11 port 11 includes p114, which is an input-only port, and p110 to p113, which comprise an i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor c an be connected to bits 0 to 3 in 1-bit units (software pull- up function). p11 can be read/written in 1-bit or 8-bit units. however, bit 4 can only be read. after reset: 00h r/w address: fffff016h 7 6 5 4 3 2 1 0 p11 0 0 0 p114 p113 p112 p111 p110 p11n control of output data (in output mode) (n = 0 to 3) 0 output 0 1 output 1 p114 read pin level 0/1 read p114 pin level remark in input mode: when port 11 (p11) is read, the pin levels at that time are read. writing to p11 writes the values to that register. this does not affect the input pins. in output mode: when port 11 (p11) is read, t he p11 values are read. writing to p11 writes the values to that register, and those values ar e immediately output (except p114). port 11 includes the following alternate functions. table 14-11. alternate functions of port 11 pin name alternate function i/o pull note remark port 11 p110 a1 i/o yes ? p111 a2 p112 a3 p113 a4 p114 xt1 input no also used as subclock (xt1) note software pull-up function
chapter 14 port function user?s manual u12768ej4v1ud 388 (1) function of p11 pins port 11 is a 5-bit (total) port that includes p114, which is an input-only por t, and p110 to p113, which comprise an i/o port for which i/o settings can be controlled in 1-bit units. in output mode, the values set to each bit (b it 0 to bit 3) are output to port 11 (p11). when using this port in input mode, t he pin statuses can be read by reading p 11. also, the p11 (output latch) values can be read by reading p11 while in output mode (bit 0 to bit 3 only). a pull-up resistor can be connected in 1-bit units for p110 to p113 when specified via pull-up resistor option register 11 (pu11). when using the alternate-function a1 to a4 pins, se t the pin functions via t he memory address output mode register (mam). at this time, be sure to set pm11 (pm110 to pm113) to 0. when a reset is input, the settings are initialized to input mode. caution because the p114/xt1 pin is in ternally connected to the xt2 pi n via a circuit, the p114/xt1 and xt2 pins will interfere with each other, even when the subclock is not be ing used. therefore, leave the xt2 pin open when not using the subclock. (2) control registers (a) port 11 mode register (pm11) pm11 can be read/written in 1-bit or 8-bit units. after reset: 1fh r/w address: fffff036h 7 6 5 4 3 2 1 0 pm11 0 0 0 1 pm113 pm112 pm111 pm110 pm11n control of i/o mode (n = 0 to 3) 0 output mode 1 input mode (b) pull-up resistor option register 11 (pu11) pu11 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff096h 7 6 5 4 3 2 1 0 pu11 0 0 0 0 pu113 pu112 pu111 pu110 pu11n control of on-chip pull-up resistor connection (n = 0 to 3) 0 do not connect 1 connect
chapter 14 port function user?s manual u12768ej4v1ud 389 (3) block diagrams (port 11) figure 14-19. block di agram of p110 to p113 remarks 1. pu11: pull-up resistor option register 11 pm11: port 11 mode register rd: read signal of port 11 wr: write signal of port 11 2. n = 0 to 3 x = 1 to 4 figure 14-20. block diagram of p114 rd alternate function internal bus p114/xt1 remark rd: read signal of port 11 wr pu pu11n pm11n pu11 output latch (p11n) alternate function selector internal bus v dd p-ch p11n/a x pm11 rd wr port wr pm
chapter 14 port function user?s manual u12768ej4v1ud 390 14.2.11 port 12 port 12 is a 1-bit i/o port. after reset: 00h r/w address: fffff018h 7 6 5 4 3 2 1 0 pu12 0 0 0 0 0 0 0 p120 p120 control of output data (in output mode) 0 output 0 1 output 1 remark in input mode: when port 12 (p12) is r ead, the pin levels at that time ar e read. writing to p12 writes the values to that register. this does not affect the input pins. in output mode: when port 12 (p12) is read, the p12 values are read. writ ing to p12 writes the values to that register, and those val ues are immediately output. port 12 includes the follo wing alternate function. table 14-12. alternate function of port 12 pin name alternate function i/o pull note remark port 12 p120 wait i/o no ? note software pull-up function (1) function of p12 pin port 12 is a 1-bit i/o port for which i/o settings can be cont rolled in 1-bit units. i/o settings are controlled via the port 12 mode register (pm12). in output mode, the set val ue is output to port 12 (p12). when using this port in input mode, the pin status can be read by reading p12. also, the p 12 (output latch) value can be read by reading p12 while in output mode. when using the alternate-function wait pin, set the pin function via the port 12 mode control register (pmc12). when a reset is input, the settings are initialized to input mode.
chapter 14 port function user?s manual u12768ej4v1ud 391 (2) control registers (a) port 12 mode register (pm12) pm12 can be read/written in 1-bit or 8-bit units. after reset: 01h r/w address: fffff038h 7 6 5 4 3 2 1 0 pm12 0 0 0 0 0 0 0 pm120 p120 control of input mode 0 output mode 1 input mode (b) port 12 mode control register (pmc12) pmc12 can be read/written in 1-bit or 8-bit units. after reset: 00h r/w address: fffff058h 7 6 5 4 3 2 1 0 pmc12 0 0 0 0 0 0 0 pmc120 pmc120 switching of alternate function 0 use as port mode 1 use as wait pin
chapter 14 port function user?s manual u12768ej4v1ud 392 (3) block diagram (port 12) figure 14-21. block diagram of p120 remark pm12: port 12 mode register pmc12: port 12 mode control register rd: read signal of port 12 wr: write signal of port 12 rd selector internal bus wr port wr pm wr pmc pm120 pm12 alternate function output latch (p120) pmc120 pmc12 p120/wait
chapter 14 port function user?s manual u12768ej4v1ud 393 14.3 setting when port pin is used as alternate function when a port pin is used for an alternate function, set t he port n mode register (pm0 to pm6 and pm9 to pm12) and output latch as shown below. table 14-13. setting when port pin is used for alternate function (1/3) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p00 nmi input pm00 = 1 setting not needed for p00 ? p01 intp0 input pm01 = 1 setting not needed for p01 ? p02 intp1 input pm02 = 1 setting not needed for p02 ? p03 intp2 input pm03 = 1 setting not needed for p03 ? p04 intp3 input pm04 = 1 setting not needed for p04 ? intp4 input p05 adtrg input pm05 = 1 setting not needed for p05 ? intp5 input p06 rtptrg input pm06 = 1 setting not needed for p06 ? p07 intp6 input pm07 = 1 setting not needed for p07 ? si0 input pm10 = 1 setting not needed for p10 ? p10 sda note i/o pm10 = 0 p10 = 0 pf10 = 1 p11 so0 output pm11 = 0 p11 = 0 ? input pm12 = 1 setting not needed for p12 sck0 output ? p12 scl note i/o pm12 = 0 p12 = 0 pf12 = 1 si1 input p13 rxd0 input pm13 = 1 setting not needed for p13 ? so1 output p14 txd0 output pm14 = 0 p14 = 0 ? input pm15 = 1 setting not needed for p15 sck1 output pm15 = 0 p15 = 0 p15 asck0 input pm15 = 1 setting not needed for p15 ? note pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and 70f3017ay only
chapter 14 port function user?s manual u12768ej4v1ud 394 table 14-13. setting when port pin is used as alternate function (2/3) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p20 si2 input pm20 = 1 setting not needed for p20 ? p21 so2 output pm21 = 0 p21 = 0 ? input pm22 = 1 setting not needed for p22 p22 sck2 output pm22 = 0 p22 = 0 ? p23 rxd1 input pm23 = 1 setting not needed for p23 ? p24 txd1 output pm24 = 0 p24 = 0 ? p25 asck1 input pm25 = 1 setting not needed for p25 ? ti2 input pm26 = 1 setting not needed for p26 p26 to2 output pm26 = 0 p26 = 0 ? ti3 input pm27 = 1 setting not needed for p27 p27 to3 output pm27 = 0 p27 = 0 ? p30 ti00 input pm30 = 1 setting not needed for p30 ? p31 ti01 input pm31 = 1 setting not needed for p31 ? p32 ti10 input pm32 = 1 setting not needed for p32 ? p33 ti11 input pm33 = 1 setting not needed for p33 ? to0 output ? p34 a13 output pm34 = 0 p34 = 0 refer to 3.4.6 (2) (mam) to1 output ? p35 a14 output pm35 = 0 p35 = 0 refer to 3.4.6 (2) (mam) ti4 input pm36 = 1 setting not needed for p36 to4 output ? p36 a15 output pm36 = 0 p36 = 0 refer to 3.4.6 (2) (mam) ti5 input pm37 = 1 setting not needed for p37 p37 to5 output pm37 = 0 p37 = 0 ? p40 to p47 ad0 to ad7 i/o setting not needed for pm40 to pm47 setting not needed for p40 to p47 refer to 3.4.6 (1) (mm) note pd703035y and 70f3035y only
chapter 14 port function user?s manual u12768ej4v1ud 395 table 14-13. setting when port pin is used as alternate function (3/3) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p50 to p57 ad8 to ad15 i/o setting not needed for pm50 to pm57 setting not needed for p50 to p57 refer to 3.4.6 (1) (mm) p60 to p65 a16 to a21 output setting not needed for pm60 to pm65 setting not needed for p60 to p65 refer to 3.4.6(1) (mm) p70 to p77 ani0 to ani7 input none setting not needed for p70 to p77 ? p80 to p83 ani8 to ani11 input none setting not needed for p80 to p83 ? lben output p90 wrl output setting not needed for pm90 setting not needed for p90 refer to 3.4.6 (1) (mm) p91 uben output setting not needed for pm91 setting not needed for p91 refer to 3.4.6 (1) (mm) r/w output p92 wrh output setting not needed for pm92 setting not needed for p92 refer to 3.4.6 (1) (mm) dstb output p93 rd output setting not needed for pm93 p93 = 1 refer to 3.4.6 (1) (mm) p94 astb output setting not needed for pm94 p94 = 1 refer to 3.4.6 (1) (mm) p95 hldak output setting not needed for pm95 setting not needed for p95 refer to 3.4.6 (1) (mm) p96 hldrq input setting not needed for pm96 setting not needed for p96 refer to 3.4.6 (1) (mm) rtp0 to rtp7 output ? p100 to p107 a5 to a12 output pm100 to pm107 = 0 p 100 to p107 = 0 refer to 3.4.6 (2) (mam) p110 to p113 a1 to a4 output pm 110 to pm113 = 0 p110 to p113 = 0 refer to 3.4.6 (2) (mam) p114 xt1 input n one setting not needed for p114 ? p120 wait input pm 120 = 1 setting not needed for p120 pmc120 = 1 (pmc12) caution when changing the output level of port 0 by se tting the of port function output mode of port 0, the interrupt request flag will be set because port 0 also has an alternate function as an external interrupt request input. therefore , be sure to set the corresponding interrupt mask flag to 1 before using the output mode. mark pmnx bit of pmn register and pnx bit of pn n: 0 (x = 0 to 7) n: 1 (x = 0 to 5) n: 2 (x = 0 to 7) n: 3 (x = 0 to 7) n: 4 (x = 0 to 7) n: 5 (x = 0 to 7) n: 6 (x = 0 to 5) n: 7 (x = 0 to 7) n: 8 (x = 0 to 3) n: 9 (x = 0 to 6) n: 10 (x = 0 to 7) n: 11 (x = 0 to 4) n: 12 (x = 0)
chapter 14 port function user?s manual u12768ej4v1ud 396 14.4 operation of port function the operation of a port differs depending on whether the port is in the input or output mode, as described below. 14.4.1 writing data to i/o port (1) in output mode a value can be written to the output la tch by using a transfer instruction. the contents of t he output latch are output from the pin. once data has been written to the output latch, it is retained until new data is written to the output latch. (2) in input mode a value can be written to the output la tch by using a transfer instruction. because the output buffer is off, however, the status of the pin does not change. once data has been written to the output latch, it is retained until new dat a is written to the output latch. caution a bit manipulation instruction (clr1, set 1, not1) manipulates 1 bi t but accesses a por t in 8-bit units. if this instruction is executed to mani pulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, are overwritten to the current input pin status and become undefined. 14.4.2 reading data from i/o port (1) in output mode the contents of the output latch can be read by using a transfer inst ruction. the contents of the output latch do not change. (2) in input mode the status of the pin can be read by using a transfer instruction. the contents of the out put latch do not change.
user?s manual u12768ej4v1ud 397 chapter 15 reset function 15.1 general when a low level is input to the reset pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. in addition, oscillation of the main clock is stopped dur ing the reset period, although oscillation of the subclock continues. when the input at the reset pin changes from low level to high leve l, the reset status is released and the cpu resumes program execution. the c ontents of the various r egisters should be initializ ed within the program as necessary. an on-chip noise eliminator uses analog delay to pr event noise-related malfuncti on at the reset pin. 15.2 pin operations during the system reset period, almost all pins are se t to high impedance (all pins except for reset, x2, xt2, av ref , v dd , v ss , av dd , av ss , bv dd , bv ss , and ic/v pp ). accordingly, if connected to an external memory device, be sure to attach a pull-up (or pull-down) resistor to each pin of ports 3 to 6 and 9 to 11. if such a resistor is not attached, these pins will be se t to high impedance, which could damage the data in memory devices. likewis e, make sure the pins are handled so as to prevent a similar effect at the signal outputs of on-chip peripher al i/o functions and output ports. figure 15-1. system reset timing analog delay eliminated as noise hi-z x1 analog delay 26.2 ms (@ 20 mhz operation) reset internal system reset signal reset is acknowledged reset is released oscillation stabilization time analog delay
user?s manual u12768ej4v1ud 398 chapter 16 flash memory the following products are the flash memory versions of the v850/sa1. caution the flash memory version and mask rom versi on differ in noise immunity and noise radiation. if replacing a flash memory version with a mask rom version when changing from trial production to mass production, make a thorough eval uation by using the cs model (not es model) of the mask rom version. pd70f3015b, 70f3015by: 128 kb flash memory versions pd70f3017a, 70f3017ay: 256 kb flash memory versions in the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock in the same way as the mask rom version. writing to flash memory can be performed with the memo ry mounted on the target syst em (on board). a dedicated flash programmer is connected to the target system to perform writing. the following can be considered as the development environment and app lications using flash memory. ? software can be altered after the v850/sa1 is solder-mounted on the target system. ? small scale production of various models is made easier by differentiating software. ? data adjustment in starting mass production is made easier. 16.1 features ? 4-byte/1-clock access (in instruction fetch access) ? all area one-shot er ase/area-unit erase ( pd70f3017a, 70f3017ay only) ? communication via serial interfac e with the dedicated flash programmer ? erase/write voltage: v pp = 7.8 v ? on-board programming ? flash memory programming by self-programming is possible in area units (128 kb) (all areas in the pd70f3015b, 70f3015by) 16.1.1 erasing unit the erasing unit differs depending on the product. (1) pd70f3015b, 70f3015by the erasing units for 128 kb flash memory versions are shown below. (a) all area one-shot erase the area of xx000000h to xx01ffffh can be erased in one shot.
chapter 16 flash memory user?s manual u12768ej4v1ud 399 (2) pd70f3017a, 70f3017ay the erasing units for 256 kb flash memory versions are shown below. (a) all area one-shot erase the area of xx000000h to xx03ffffh can be erased in one shot. (b) area erase erasure can be performed in area units (there are two 128 kb unit areas). area 0: the area of xx000000h to xx01ffffh (128 kb) is erased area 1: the area of xx020000h to xx03ffffh (128 kb) is erased 16.2 writing by flash programmer writing can be performed either on-board or off-board by the dedicated flash programmer. (1) on-board programming the contents of the flash memory ar e rewritten after the v850/sa1 is mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to the flash memory is performed by the dedicat ed program adapter (fa series), etc., before mounting the v850/sa1 on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd.
chapter 16 flash memory user?s manual u12768ej4v1ud 400 figure 16-1. wiring example of v850/sa1 flash writing adapter (fa100gc-8eu) pd70f3015b, pd70f3015by, pd70f3017a, pd70f3017ay si so sck /reset v pp reserve/hs x1 vdd gnd gnd vdd gnd vdd vdd gnd 31 32 34 36 37 56 73 72 71 55 connect to vdd. connect to gnd. 99 94 95 96 718 6 1 remarks 1. pins not described above should be handled a ccording to the recommended connection of unused pins (refer to 2.4 pin i/o circuits and recomme nded connection of unused pins ). when connecting to v dd via a resistor, connecting a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 100-pin plastic lqfp package. 3. this figure indicates the connecti on when csi supporting handshake is used.
chapter 16 flash memory user?s manual u12768ej4v1ud 401 table 16-1. wiring table of v850/sa1 flash writing adapter (fa-100gc-8eu) flash programmer (pg-fp3/pg-fp4) connection pin when using csi0 + hs when us ing csi0 when using uart0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal p11/so0 95 p11/so0 95 p14/txd0 98 so/txd output transmit signal p10/si0 94 p10/si0 94 p13/rxd0 97 sck output transfer clock p12/sck0 96 p12/sck0 68 unnecessary unnecessary clk output clock to v850/sa1 x1 36 x1 36 x1 36 /reset output reset signal reset 31 reset 31 reset 31 vpp output writing voltage v pp 18 v pp 18 v pp 18 hs input handshake signal of csi0 + hs communication p15 99 unnecessary unnecessary unnecessary unnecessary v dd 6, 34 v dd 6, 34 v dd 6, 34 av dd 71 av dd 71 av dd 71 vdd ? vdd voltage generation/voltage monitoring bv dd 55 bv dd 55 bv dd 55 v ss 7, 37 v ss 7, 37 v ss 7, 37 av ss 72 av ss 72 av ss 72 av ref 73 av ref 73 av ref 73 gnd ? ground bv ss 56 bv ss 56 bv ss 56
chapter 16 flash memory user?s manual u12768ej4v1ud 402 figure 16-2. wiring example of v850/sa1 flash writing adapter (fa-121f1-ea6) pd70f3017a, pd70f3017ay si so sck /reset v pp reserve/hs x1 vdd gnd gnd vdd gnd vdd vdd gnd b11 b5 a13 c13 c11 b4 a5 d4 a2 b3 d1 d3 e2 n4 m7 m4 n5 n7 a1 a3 c3 d2 j2 j1 l11 l13 e11 d12 l12 k13 e12 d13 l3 m6 b12 connect to vdd. connect to gnd. l4 n6 l5 m8 d11 remarks 1. pins not described above should be handled a ccording to the recommended connection of unused pins (refer to 2.4 pin i/o circuits and recomme nded connection of unused pins ). when connecting to v dd via a resistor, connecting a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 121-pin plastic fbga package. 3. this figure indicates the connecti on when csi supporting handshake is used.
chapter 16 flash memory user?s manual u12768ej4v1ud 403 table 16-2. wiring table of v850/sa1 flash writing adapter (fa-121f1-ea6) flash programmer (pg-fp3/pg-fp4) connection pin when using csi0 + hs when us ing csi0 when using uart0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal p11/so0 a5 p11/so0 a5 p14/txd0 b2 so/txd output transmit signal p10/si0 b5 p10/si0 b5 p13/rxd0 a4 sck output transfer clock p12/sck0 b4 p12/sck0 b4 unnecessary unnecessary clk output clock to v850/sa1 x1 m6 x1 m6 x1 m6 /reset output reset signal reset l3 reset l3 reset l3 vpp output writing voltage v pp j1, j2 v pp j1, j2 v pp j1, j2 hs input handshake signal of csi0 + hs communication p15 a2 unnecessary unnecessary unnecessary unnecessary v dd note 1 v dd note 1 v dd note 1 av dd note 2 av dd note 2 av dd note 2 vdd ? vdd voltage generation/voltage monitoring bv dd k13 bv dd k13 bv dd k13 v ss note 3 v ss note 3 v ss note 3 av ss note 4 av ss note 4 av ss note 4 av ref c13 av ref c13 av ref c13 gnd ? ground bv ss l11 to l13 bv ss l11 to l13 bv ss l11 to l13 notes 1. d1, d2, e2, l4, m4, n4 2. d11 to d13, e11 3. a3, b3, c3, d3, l5, m7, m8, n6, n7 4. a13, b11, b12, c11
chapter 16 flash memory user?s manual u12768ej4v1ud 404 16.3 programming environment the following shows the environment r equired for writing programs to t he flash memory of the v850/sa1. figure 16-3. environment for wr iting programs to flash memory rs-232-c host machine v850/sa1 dedicated flash programmer v ss v pp v dd reset uart0/csi0 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y yy xxxxx xxxxxx xxxx x xx x yy yy s tat v e a host machine is required for contro lling the dedicated flash programmer. uart0 or csi0 is used for the interface between t he dedicated flash programmer and the v850/sa1 to perform writing, erasing, etc. a dedica ted program adapter (fa series) is required for off-board writing. 16.4 communication system the communication between the dedica ted flash programmer and the v850/ sa1 is performed by serial communication using uart0 or csi0. (1) uart0 transfer rate: 9600 to 76800 bps figure 16-4. communication with de dicated flash programmer (uart0) v850/sa1 reset gnd v dd v pp dedicated flash programmer txd rxd reset v ss v dd v pp rxd0 txd0 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y xxxxx xxxxxx xxxx x xx x y y y y statve
chapter 16 flash memory user?s manual u12768ej4v1ud 405 (2) csi0 serial clock: up to 1 mhz (msb first) figure 16-5. communication with de dicated flash programmer (csi0) v850/sa1 dedicated flash programmer reset gnd v dd v pp so si reset v ss v dd v pp si0 so0 sck sck0 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y y y xxxxx xxxxxx xxxx x x x x y yyy statve (3) csi0 + hs serial clock: up to 1 mhz (msb first) figure 16-6. communication with dedi cated flash programmer (csi0 + hs) dedicated flash programmer v850/sa1 v pp v dd v ss reset si0 so0 sck0 p15 v pp v dd gnd reset so si sck hs pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve
chapter 16 flash memory user?s manual u12768ej4v1ud 406 the dedicated flash programmer out puts the transfer clock, and the v850/sa1 operates as a slave. when the pg-fp3 or pg-fp4 is used as the dedicated flash programmer, it generates the signals shown in table 16-3 to the v850/sa1. for the details, refer to pg-fp3 user?s manual (u13502e) , or pg-fp4 user?s manual (u15260e) . table 16-3. signal generation of dedicat ed flash programmer (pg-fp3 or pg-fp4) pg-fp3 or pg-fp4 v850/sa1 measures when connected signal name i/o pin function pin name csi0 uart0 csi0 + hs v pp output writing voltage v pp v dd i/o v dd voltage generation/ voltage monitoring v dd gnd ? ground v ss clk note output clock output to v850/sa1 x1 { { { reset output reset signal reset si/rxd input receive signal so0/txd0 so/txd output transmit signal si0/rxd0 sck output transfer clock sck0 hs input handshake signal of csi0 + hs communication p15 note supply clocks on the target board. remark : always connected { : if this signal is generated on the target board, it does not need to be connected. : does not need to be connected
chapter 16 flash memory user?s manual u12768ej4v1ud 407 16.5 pin connection when performing on-board writing, install a connector on the target syst em to connect to the dedicated flash programmer. also, incorporate a func tion on-board to switch from the norma l operation mode to the flash memory programming mode. when switched to the flash memory pr ogramming mode, all the pins not us ed for the flash memory programming become the same status as that immediately after reset. therefor e, all the ports bec ome output high-impedance status, so that pin handling is r equired when the external device does not acknowledge the output high-impedance status. 16.5.1 v pp pin in the normal operation mode, 0 v is input to v pp pin. in the flash memory programming mode, 7.8 v writing voltage is supplied to v pp pin. the following shows an example of the connection of v pp pin. figure 16-7. connection example of v pp pin v pp dedicated flash programmer connection pin pull-down resistor ( r vpp ) v850/sa1 16.5.2 serial interface pin the following shows the pins us ed by each serial interface. table 16-4. pins used by each serial interface serial interface pins used csi0 so0, si0, sck0 csi0 + hs so0, si0, sck0, p15 uart0 txd0, rxd0 when connecting a dedicated flash programmer to a serial interface pin that is c onnected to other devices on- board, care should be taken to avoid conflict of signals and malfunction of t he other devices, etc.
chapter 16 flash memory user?s manual u12768ej4v1ud 408 (1) conflict of signals when connecting a dedicated flash progra mmer (output) to a serial interfac e pin (input) that is connected to another device (output), c onflict of signals occurs. to avoid the conf lict of signals, isolat e the connection to the other device or set the other devic e to the output hi gh-impedance status. figure 16-8. conflict of signals (serial interface input pin) v850/sa1 other device output pin conflict of signals input pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. therefore, isolate the signals on the other device side. dedicated flash programmer connection pin (2) malfunction of the other device when connecting a dedicated flash programmer (output or input) to a serial inte rface pin (input or output) that is connected to another device (input ), the signal output to t he other device may cause t he device to malfunction. to avoid this, isolate the connection to the other device or make the setting so that the input si gnal to the other device is ignored. figure 16-9. malfunction of other device v850/sa1 pin in the flash memory programming mode, if the signal the v850/sa1 outputs affects the other device, isolate the signal on the other device side. other device in p ut p in dedicated flash programmer connection pin v850/sa1 pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. other device input pin dedicated flash programmer connection pin
chapter 16 flash memory user?s manual u12768ej4v1ud 409 16.5.3 reset pin when connecting the reset signals of the dedicated flash programmer to the r eset pin that is connected to the reset signal generator on-board, conflict of signals occurs. to avoid the conflict of signal s, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memo ry programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 16-10. conflict of signals (reset pin) reset v850/sa1 reset signal generator output pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator. dedicated flash programmer connection pin 16.5.4 port pin (including nmi) when the flash memory programming mode is set, all the por t pins except the pins that communicate with the dedicated flash programmer become out put high-impedance status. if problem s such as disabling output high- impedance status should occur to the external dev ices connected to the port, connect them to v dd or v ss via resistors. 16.5.5 other signal pins connect x1, x2, xt2, and av ref to the same status as that in the normal operation mode. 16.5.6 power supply supply the same power supply (v dd , v ss , av dd , av ss , bv dd , bv ss ) as when in normal operation mode. in addition, connect v dd and v ss to v dd and gnd of the dedicated flash programmer (v dd of the dedicated flash programmer has a power supply monitoring function).
chapter 16 flash memory user?s manual u12768ej4v1ud 410 16.6 programming method 16.6.1 flash memory control the following shows the procedure fo r manipulating the flash memory. figure 16-11. manipulation procedure of flash memory su pp l y reset p ulse switch to flash memory programming mode select communication system manipulate flash memory end? no yes end start 16.6.2 flash memory programming mode when rewriting the contents of the flash memory using the dedicated fl ash programmer, set the v850/sa1 in the flash memory programming mode. when switching modes, set v pp pin before releasing reset. when performing on-board writing, c hange modes using a jumper, etc.
chapter 16 flash memory user?s manual u12768ej4v1ud 411 figure 16-12. flash memory programming mode v pp reset flash memory programming mode 7.8 v 3 v 0 v 12 ? n v pp operation mode 0 v normal operation mode 7.8 v flash memory programming mode 16.6.3 selection of communication mode in the v850/sa1, the communication mode is select ed by inputting a pulse (16 pulses max.) to v pp pin after switching to the flash memo ry programming mode. the v pp pulse is generated by the dedicated flash programmer. the following shows the relationship between t he number of pulses and the communication mode. table 16-5. list of communication modes v pp pulse communication mode remarks 0 csi0 v850/sa1 performs slave operation, msb first 3 csi0 + hs v850/sa1 performs slave operation, msb first 8 uart0 communication rate: 9600 bps (at reset), lsb first other rfu setting prohibited caution when uart0 is selected, th e receive clock is calcu lated based on the reset command sent from the dedicated flash progra mmer after receiving the v pp pulse. 16.6.4 communication command the v850/sa1 communicates with the dedicated flash programmer by means of commands. the command sent from the dedicated flash programmer to the v850/sa1 is called a ?command?. the response signal sent from the v850/sa1 to the dedicated flash progr ammer is called a ?response command?. figure 16-13. communication command v850/sa1 command dedicated flash programmer response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y y y xxxxx xxxxxx xxxx x x x x y yy y statve
chapter 16 flash memory user?s manual u12768ej4v1ud 412 the following shows the commands for flash memory contro l of the v850/sa1. all of these commands are issued from the dedicated flash programmer, and the v850/sa1 performs the vari ous processing corresponding to the commands. table 16-6. commands for flash memory control category command name function one-shot verify command compares t he contents of the entire memory and the input data. verify area verify command compares the contents of the specified area and the input data. one-shot erase command erases the contents of the entire memory. area erase command erases the c ontents of the specified area. erase write back command writes back the contents which is overerased. one-shot blank check command checks t he erase state of the entire memory. blank check area blank check command checks the er ase state of the specified area. high-speed write command writes data by the specification of the write address and the number of bytes to be written, and executes a verify check. data write continuous write command writes data from the address following the high- speed write command executed immediately before, and executes a verify check. status read out command acquires the status of operations. oscillating frequency setting command sets the oscillation frequency. erasing time setting command sets the erasing time of one-shot erase. writing time setting command sets the writing time of data write. write back time setting command sets the write back time. baud rate setting command sets the baud rate when using uart. silicon signature command reads outs the silicon signature information. system setting and control reset command escapes from each state. the v850/sa1 sends back response commands to the comm ands issued from the dedica ted flash programmer. the following shows the response commands the v850/sa1 sends out. table 16-7. response commands response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc. 16.6.5 resources used the resources used in the flash memo ry programming mode are all the ffe000h to ffe7ffh area of the internal ram and all the registers. the ffe800h to ffefffh area of the internal ram re tains data as long as the power is on. the registers that ar e initialized by reset are changed to the default values.
chapter 16 flash memory user?s manual u12768ej4v1ud 413 16.7 flash memory programming by self-programming the v850/sa1 supports a self-programming function to rewrite the flash memory using a user program. by using this function, the flash memory can be rewritten by a user application. this self-programming function can also be used to upgrade the program in the field. 16.7.1 outline of self-programming self-programming implements erasure and writing of the flash memory by calling the self-programming function (device?s internal processing) on the program placed in other than the inter nal rom area (000000h to 0fffffh). to place the program in the block 0 s pace and internal rom area, copy the program to areas other than 000000h to 0fffffh (e.g. internal ram area) and execute the program to call the self -programming function. to call the self-programming functi on, change the operating m ode from normal mode to self-programming mode using the flash programming mode control register (flpmc). figure 16-14. outline of self-programming (1/2) (a) pd70f3015b, 70f3015by 128 kb flash memory 00000h 1ffffh erase area (128 kb) flash memory normal operation mode self-programming mode 00000h 1ffffh flpmc 02h flpmc 00h self-programming function (delete/write routine incorporated)
chapter 16 flash memory user?s manual u12768ej4v1ud 414 figure 16-14. outline of self-programming (2/2) (b) pd70f3017a, 70f3017ay 256 kb flash memory 00000h 3ffffh erase area note (128 kb) erase area note (128 kb) flash memory normal operation mode self-programming mode 00000h 3ffffh flpmc 02h flpmc 00h self-programming function (delete/write routine incorporated) note data is deleted in area units (128 kb). 16.7.2 self-programming function the v850/sa1 provides self-progr amming functions, as shown below. by combining these functions, erasing/writing flash me mory becomes possible. table 16-8. function list type function name function erase area erase erases the specified area. continuous write in word units continuously writes the specified memory contents from the specified flash memory address, for the number of words specified in 4-byte units. write prewrite writes 0 to flas h memory before erasure. erase verify checks whether an ov ererase occurred after erasure. erase byte verify checks whether erasure is complete. check internal verify checks whether the signal level of the post-write data in flash memory is appropriate. write back area write back writes back the flash memory area in which an overerase occurred. acquire information flash memory information read reads out information about flash memory.
chapter 16 flash memory user?s manual u12768ej4v1ud 415 16.7.3 outline of sel f-programming interface to execute self-programming using t he self-programming interface, the env ironmental conditions of the hardware and software for manipulating the fl ash memory must be satisfied. it is assumed that the self-programming interface is used in an assembly language. (1) entry program this program is used to call the in ternal processing of the device. it is a part of the application progr am, and must be executed in memory other than the internal rom area (flash memory). (2) device internal processing this is manipulation of the flash me mory executed inside the device. this processing manipulates the flash memory after it has been called by the entry program. (3) ram parameter this is a ram area to which the par ameters necessary for self-programmi ng, such as write time and erase time, are written. it is set by the application progr am and referenced by the dev ice internal processing. the self-programming interface is outlined below. figure 16-15. outline of self-programming interface application program entry program ram parameter device internal processing flash memory self-programming interface flash-memory manipulation 16.7.4 hardware environment to write or erase the flash memory, a high voltage must be applied to the v pp pin. to execute self-programming, a circuit that can gener ate a write voltage (v pp ) and that can be controlled by softw are is necessary on the application system. an example of a circuit that c an select a voltage to be applied to the v pp pin by manipulating a port is shown below.
chapter 16 flash memory user?s manual u12768ej4v1ud 416 figure 16-16. example of self-p rogramming circuit configuration v dd = 3.3 0.3 v v850/sa1 v dd v ss v pp output port ic for power supply output input on/off v ss 10 k ? 10 k ? v in (v pp = 7.8 0.3 v) the voltage applied to the v pp pin must satisfy the following conditions. ? hold the voltage applied to the v pp pin at 0 v in the normal operation mode and hold the v pp voltage only while the flash memory is being manipulated. ? the v pp voltage must be stable from befor e manipulation of the flash memo ry starts until manipulation is complete. cautions 1. apply 0 v to the v pp pin when reset is released. 2. implement self-programming in single-chip mode. 3. apply the voltage to the v pp pin in the entry program. 4. if both writing and erasing are executed by using the self-programming function and flash memory programmer on the target board, be sure to communicate with the programmer using csi0 (do not use the ha ndshake-supporting csi and uart0). figure 16-17. timing to apply voltage to v pp pin flash memory manipulation reset signal v pp signal v pp 0 v v dd 0 v
chapter 16 flash memory user?s manual u12768ej4v1ud 417 16.7.5 software environment the following conditions must be satisfi ed before using the entry program to call the device internal processing. table 16-9. software environmental conditions item description location of entry program execute the entry program in memory other than the flash memory area. the device internal proce ssing cannot be directly called by the pr ogram that is executed on the flash memory. execution status of program the device internal processing c annot be called while an interrupt is being serviced (np bit of psw = 0, id bit of psw = 1). masking interrupts mask all the maskable interrupts used. mask each interrupt by using the corresponding interrupt control register. mask the maskable interrupts even when the id bi t of the psw = 1 (interrupts are disabled). manipulation of v pp voltage stabilize the voltage applied to the v pp pin (v pp voltage) before starting manipulation of the flash memory. after completion of manipulation, return the voltage of the v pp pin to 0 v. initialization of internal timer do not use 16-bit timer 0 while the flash memory is being manipulated. because 16-bit timer 0 is initializ ed after the flash memory has been us ed, initialize the timer with the application program to use the timer again. stopping reset signal input do not input the reset signal while t he flash memory is being manipulated. if the reset signal is input while the flash memory is being manipulated, the contents of the flash memory under manipulation become undefined. stopping nmi signal input do not input the nmi signal while the flash memory is being manipulated. if the nmi signal is input while the flash memory is being manipulated, the flash memory may not be correctly manipulated by the dev ice internal processing. if an nmi occurs while the device internal processi ng is in progress, the occurrence of the nmi is reflected in the nmi flag of the ram parameter. if m anipulation of the flash memory is affected by the occurrence of the nmi, the function of each self-progr amming function is reflected in the return value. reserving stack area the device internal pr ocessing takes over the stack used by the user program. it is necessary that an area of 300 bytes be reserved for the stack size of the user program w hen the device internal processing is called. r3 is used as the stack pointer. saving general-purpose registers the device internal processing re writes the contents of r6 to r14, r20, and r31 (lp). save and restore these register contents as necessary.
chapter 16 flash memory user?s manual u12768ej4v1ud 418 16.7.6 self-programming function number to identify a self-programming functi on, the following numbers are assigned to the respective functions. these function numbers are used as par ameters when the device inter nal processing is called. table 16-10. self-programming function numbers function no. function name 0 to 2 rfu 3 erase verify 4 erase byte verify 5 flash information acquisition 6 rfu 7 successive write in word units 8 to 10 rfu 11 pre-write 12 successive write in word units 13 area write back 14 area erase other prohibited remark rfu: reserved for future use
chapter 16 flash memory user?s manual u12768ej4v1ud 419 16.7.7 calling parameters the arguments used to call the self-pr ogramming function are shown in the table below. in addition to these arguments, parameters such as the writ e time and erase time are set to the ram parameters indicated by ep (r30). table 16-11. calling parameters function name first argument (r6) function no. second argument (r7) third argument (r8) fourth argument (r9) return value (r10) erase verify 3 none (acts on erase manipulation area immediately before) ? ? 0: normal completion other than 0: error erase byte verify 4 verify st art address number of bytes to be verified ? 0: normal completion other than 0: error acquiring flash information 5 option number note 1 ? ? note 1 successive write in word units note 2 7 write start address note 3 start address of write source data note 3 number of words to be written (word units) 0: normal completion other than 0: error pre-write 11 write start address number of bytes to be written ? 0: normal completion other than 0: error internal verify 12 verify star t address number of bytes to be verified ? 0: normal completion other than 0: error area write back 13 none (acts on erase manipulation area immediately before) ? ? none erasing area 14 area erase start address ? ? 0: normal completion other than 0: error notes 1. see 16.7.10 flash information for details. 2. prepare write source data in memo ry other than the flash memory w hen data is written successively in word units. 3. this address must be at a 4-byte boundary. caution for all the functions, ep (r30) must i ndicate the first address of the ram parameter.
chapter 16 flash memory user?s manual u12768ej4v1ud 420 16.7.8 contents of ram parameters reserve the following 48-byte area in the internal ram or external ram for the ram parameters, and set the parameters to be input. set the base addre sses of these parameters to ep (r30). table 16-12. description of ram parameter address size i/o description ep+0 4 bytes ? for internal operations ep+4:bit 0 note 1 1 bit input internal flag 0: always set to 0 1: setting prohibited ep+4:bit 5 note 2 1 bit input operation flag (be sure to set this flag to 1 before calling the device internal processing.) 0: normal operation in progress 1: self-programming in progress ep+4:bit 7 notes 3, 4 1 bit output nmi flag 0: nmi not detected 1: nmi detected ep+8 4 bytes input step eras e time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = erase time ( s)/internal operation unit time ( s) example: if erase time is 0.2 s 0.2 1,000,000/100 = 2,000 (integer operation) ep+0xc 4 bytes input write back time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = write back time ( s)/internal operation unit time ( s) example: if write back time is 1 ms 1 1,000/100 = 10 (integer operation) ep+0x10 2 bytes input timer set value for creating internal operation unit time (unsigned 2 bytes) write a set value that makes the value of 16- bit timer 0 the internal operation unit time (100 s). set value = operating frequency (hz)/1,000,000 internal operation unit time ( s)/ timer division ratio (2) + 1 note 5 example: if the operating frequency is 20 mhz 20,000,000/1,000,000 100/2 + 1 = 1,001 (integer operation) ep+0x12 2 bytes input timer set value for creating write time (unsigned 2 bytes) write a set value that makes the value of 16-bit timer 0 the write time. set value = operating frequency (hz)/write time ( s)/timer division ratio (2) + 1 note 5 example: if the operating frequency is 20 mhz and the write time is 20 s 20,000,000/1,000,000 20/2 + 1 = 201 (integer operation) ep+0x14 12 bytes ? for internal operations notes 1. bit 0 of the address of ep+4 (least significant bit is bit 0.) 2. 5th bit of address of ep+4 (least significant bit is bit 0.) 3. 7th bit of address of ep+4 (least significant bit is bit 0.) 4. clear the nmi flag by the user program because it is not cleared by the device internal processing. 5. the device internal processing sets this value minus 1 to the timer. becaus e the fraction is rounded up, add 1 as indicated by the ex pression of the set value. caution be sure to reserve the ram parameter area at a 4-byte boundary.
chapter 16 flash memory user?s manual u12768ej4v1ud 421 16.7.9 errors during self-programming the following errors related to manipul ation of the flash memory may occur during self-programming. an error occurs if the return value (r 10) of each function is not 0. table 16-13. errors during self-programming error function description overerase error erase verify excessive erasure occurs. undererase error (blank check error) erase byte verify erasur e is insufficient. addi tional erase operation is needed. verify error successive writing in word units the written data cannot be correctly read. either an attempt has been made to write to flash memory that has not been erased, or writing is not sufficient. internal verify error internal verify the written data is not at the correct signal level. caution the overerase error and undererase error may si multaneously occur in th e entire flash memory. 16.7.10 flash information for the flash information acquisition function (function no. 0), the option number (r7 ) to be specified and the contents of the return value (r10) are as follows. to acquire all flash information, call the function as many times as required in accordance with the format shown below. table 16-14. flash information option no. (r7) return value (r10) 0 specification prohibited 1 bit representation of return val ue (msb: bit 31) ffffffffffffffff aaaaaaaabbbbbbbb (lsb: bit 0) bits 31 to 16: ffffffffffffffff (reserved for future use) mask bits 31 to 16 because they are not normally 0. bits 15 to 8: aaaaaaaa (number of areas) (unsigned 8 bits) bits 7 to 0: ffffffff (reserved for future use) mask bits 7 to 0 because they are not normally 0. 2 rfu 3 rfu : : : : offset number + 1 rfu offset number + 2 end address of area 0 offset number + 3 end address of area 1 cautions 1. the start address of area 0 is 0. the ?end address + 1? of the preceding area is the start address of the next area. 2. the flash information acquisition functi on does not check values such as the maximum number of areas specified by the argument of an option. if an illegal value is specified, an undefined value is returned. remark rfu: reserved for future use
chapter 16 flash memory user?s manual u12768ej4v1ud 422 16.7.11 area number the area numbers and memory map of the v850/sa1 are shown below. figure 16-18. area configuration (a) pd70f3015b, 70f3015by area 0 (128 kb) 0 x 0 0 0 0 0 (start address of area 0) 0 x 1 f f f f (end address of area 0) (b) pd70f3017a, 70f3017ay area 1 (128 kb) area 0 (128 kb) 0 x 3 f f f f (end address of area 1) 0 x 0 0 0 0 0 (start address of area 0) 0 x 2 0 0 0 0 (start address of area 1) 0 x 1 f f f f (end address of area 0)
chapter 16 flash memory user?s manual u12768ej4v1ud 423 16.7.12 flash programming mode control register (flpmc) the flash memory mode control register (flpmc) is a register used to enable/ disable writing to flash memory and to specify the self-programming mode. this register can be read/written in 8-bit or 1-bit units (the vpp bit (bit 2) is read-only). cautions 1. be sure to transfer control to th e internal ram or external memory beforehand to manipulate the flspm bit. however, in on- board programming mode set by the flash programmer, the specification of flspm bit is ignored. 2. be sure to set bits 0 and 5 to 7 to 0 and bit 4 to 1. flpmc address fffff8d4h after reset note 18h/38h/1ch/3ch 76543210 0 flspm vpp vppdis 1 0 0 0 note 18h/38h: when writing volt age is not applied to the v pp pin 1ch/3ch: when writing vo ltage is applied to the v pp pin bit position bit name function 3 vppdis v pp disable enables/disables writing/er asing on-chip flash memory . when this bit is 1, writing/erasing on-chip flas h memory is disabled even if a high voltage is applied to the v pp pin. 0: enables writing/er asing flash memory 1: disables writing/ erasing flash memory 2 vpp v pp indicates that the voltage applied to the v pp pin has reached the writing-enabled level. this bit is used to check whether writing is possible or not in the self- programming mode. 0: indicates high-voltage application is not detected (the voltage has not reached the writing voltage enable level) 1: indicates high-voltage application is detected (the voltage has reached the writing voltage enable level) 1 flspm flash self programming mode controls switching between internal rom and the self-programming interface. this bit can switch the mode between the normal mode set by the mode pin on the application system and the self-programming mode. the setting of this bit is valid only if the voltage applied to the v pp pin reaches the writing voltage enable level. 0: normal mode (for all addresses, instruction fetch is performed from on-chip flash memory) 1: self-programming mode (device in ternal processing is started.) remark because the mask rom versions ( pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 703017a, and 703017ay) do not have the flpmc register, an undefined value is read if an attempt is made to read the flpmc register.
chapter 16 flash memory user?s manual u12768ej4v1ud 424 the following sequence shows the data setting of the flpmc register. <1> disable dma operation. <2> set the psw np bit to 1 (interrupts disabled). <3> write any 8-bit data in the command register (prcmd). <4> write the set data in the flpmc regi ster (using the following instructions). ? store instruction (s t/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> return the psw np bit to 0 (interrupt disable canceled). <6> insert five nop instructions (when manipulating the flspm bit). <7> if necessary, enable dma operation. no special sequence is required when reading the flpmc register. cautions 1. if an interrupt request or a dma request is acknowledged between the time prcmd is generated (<3>) and the flpmc re gister write operation (<4>) that follows immediately after, the write operation to the flpmc register is not performed and a protection error (prerr bit of sys register is 1) may occur. therefore, set th e np bit of the psw to 1 (<2>) to disable the acknowledgement of int/nmi or to disable dma transfer. the above also applies when a bit manipul ation instruction is used to set the flpmc register. a description example is given below. [description example] ldsr rx.5 ; np bit = 1 st.b r0, prcmd [r0] ; write to prcmd st.b rd, flpmc [r0] ; flpmc register setting ldsr ry, 5 ; np bit = 0 nop ; dummy instruction (5 instructions, when manipulating flspm bit) nop nop nop nop (next instruction) ; execution routine following cancellation of . idle/software stop mode . . rx: value to be written to psw ry: value to be written back to psw rd: value to be set to flpmc when saving the value of the psw, the value of the psw prior to setting the np bit must be transferred to the ry register. cautions 2. always stop the dma pr ior to accessing speci fic registers.
chapter 16 flash memory user?s manual u12768ej4v1ud 425 16.7.13 calling device internal processing this section explains the procedure to call the dev ice internal processing from the entry program. before calling the device internal processing, make su re that all the conditions of the hardware and software environments are satisfied and that the necessary arguments and ram param eters have been set. call the device internal processing by setting the flspm bit of the flas h programming mode control regi ster (flpmc) to 1 and then executing the trap 0x1f instruct ion. the processing is always called using t he same procedure. it is assumed that the program of this interface is described in an assembly language. <1> set the flpmc register as follows: ? vppdis bit = 0 (to enable writing/erasing flash memory) ? flspm bit = 1 (to select self-programming mode) <2> clear the np bit of the psw to 0 (to enable nm is (only when nmis are used on the application)). <3> execute trap 0x1f to transfer the cont rol to the device?s internal processing. <4> set the np bit and id bit of the psw to 1 (to disable all interrupts). <5> set the value to the peripheral command register (phcmd) that is to be set to the flpmc register. <6> set the flpmc register as follows: ? vppdis bit = 1 (to disable writing/erasing flash memory) ? flspm bit = 0 (to select normal operation mode) <7> wait for the internal manipulation setup time (see 16.7.13 (5) internal manipulation setup parameter ). (1) parameter r6: first argument (sets a self-programming function number) r7: second argument r8: third argument r9: fourth argument ep: first address of ram parameter (2) return value r10: return value (return value from device internal processing of 4 bytes) ep+4:bit 7: nmi flag (flag indicating whether an nmi occurred while the device internal processing was being executed) 0: nmi did not occur while device in ternal processing was being executed. 1: nmi occurred while device inter nal processing was being executed. if an nmi occurs while control is being transferr ed to the device internal processing, the nmi request may never be reflected. because the nmi flag is not internally reset, this bit must be cleared before calling the device inte rnal processing. after the c ontrol returns from the device internal processing, nmi dummy processing can be executed by checking the status of this flag using software. (3) description transfer control to the device internal processing specified by a function number using the trap instruction. to do this, the hardware and software env ironmental conditions must be satisfi ed. even if trap 0x1f is used in the user application program, trap 0x1f is treated as another operation afte r the flpmc register has been set. therefore, use of the tr ap instruction is not rest ricted on the application.
chapter 16 flash memory user?s manual u12768ej4v1ud 426 (4) program example an example of a program in which t he entry program is executed as a s ubroutine is shown below. in this example, the return address is sav ed to the stack and then the device inte rnal processing is called. this program must be located in memory other t han the block 0 space and flash memory area. isetup 52 -- internal manipulation setup parameter entryprogram: add -4, sp -- prepare st.w lp, 0[sp] -- save return address movea lo(0x00a0), r0, r10 -- ldsr r10, 5 -- psw = np, id mov lo(0x0002), r10 -- st.b r10, prcmd[r0] -- prcmd = 2 st.b r10, flpmc[r0] -- vppdis = 0, flspm = 1 nop nop nop nop nop movea lo(0x0020), r0, r10 -- ldsr r10, 5 -- psw = id trap 0x1f -- device internal process movea lo(0x00a0), r0, r6 -- ldsr r6, 5 -- psw = np, id mov lo(0x08), r6 st.b r6, prcmd[r0] -- prcmd = 8 st.b r6, flpmc[r0] -- vppdis = 1, flspm = 0 nop nop nop nop nop mov isetup, lp -- loop time = 52 loop: divh r6, r6 -- to kill time add -1, lp -- decrement counter jne loop -- ld.w 0[sp], lp -- reload lp add 4, sp -- dispose jmp [lp] -- return to caller
chapter 16 flash memory user?s manual u12768ej4v1ud 427 (5) internal manipulation setup parameter if the self-programming mode is s witched to the normal operation mode, the v850/sa1 must wait for 100 s before it accesses the flash memory. in the program example in (4) above, the elapse of th is wait time is ensured by setting isetup to ?52? (@ 20 mhz operation). the to tal number of execution clocks in this example is 39 clocks (divh instruction (35 clocks) + add instruction (1 clock) + jne instruction (3 clocks)). ensure that a wait time of 100 s elapses by using the following expression. 39 clocks (total number of execution clocks) 50 ns (@ 20 mhz operation) 52 (isetup) = 101.4 s (wait time)
chapter 16 flash memory user?s manual u12768ej4v1ud 428 16.7.14 flow of erasing flash memory the procedure to erase the flash memo ry is illustrated below. the proce ssing of each function number must be executed in accordance with t he specified calling procedure. figure 16-19. flow of erasing flash memory ... function no. 11 ... function no. 14 ... function no. 4 ... function no. 3 ... function no. 13 ... function no. 3 ... function no. 4 erase write error undererase error set ram parameter mask interrupts pre-write erase area erase byte verify erase verify area write back erase verify clear number of times write-back is repeated erase byte verify write error? undererase? maximum number of times of repeating erasure is exceeded? maximum number of times of repeating write-back is exceeded? overerase? overerase? undererase? set v pp voltage clear v pp voltage unmask interrupts clear v pp voltage unmask interrupts normal completion clear v pp voltage unmask interrupts overerase error clear v pp voltage unmask interrupts normal completion clear v pp voltage unmask interrupts yes yes yes yes no no no yes no no no yes no yes
chapter 16 flash memory user?s manual u12768ej4v1ud 429 16.7.15 successive writing flow the procedure to write data all at once to the flash memory by using the function to successively write data in word units is illustrated below. the proce ssing of each function number must be exec uted in accordance with the specified calling procedure. figure 16-20. successive writing flow ... function no. 7 yes no successive writing mask interrupts set v pp voltage successive writing error? clear v pp voltage unmask interrupts write error clear v pp voltage unmask interrupts normal completion set ram parameter
chapter 16 flash memory user?s manual u12768ej4v1ud 430 16.7.16 internal verify flow the procedure of internal verificati on is illustrated below. the proce ssing of each function number must be executed in accordance with t he specified calling procedure. figure 16-21. internal verify flow ... function no. 12 yes no internal verify mask interrupts set v pp voltage internal verify error? clear v pp voltage unmask interrupts internal verify error clear v pp voltage unmask interrupts normal completion set ram parameter
chapter 16 flash memory user?s manual u12768ej4v1ud 431 16.7.17 flow of acquiring flash information the procedure to acquire the flash information is illustra ted below. the processing of each function number must be executed in accordance with t he specified calling procedure. figure 16-22. flow of acquiring flash information ... function no. 5 acquiring flash information mask interrupts set v pp voltage acquiring flash information clear v pp voltage unmask interrupts end set ram parameter
chapter 16 flash memory user?s manual u12768ej4v1ud 432 16.7.18 self-programming library the v850 series flash memory self programming library user?s manual is available for reference when executing self-programming. in this manual, the library uses the self-programming inte rface of the v850 series and can be used in c as a utility and as part of the application program . when using the library, thoroughly evaluate it on the application system. (1) functional outline figure 16-23 outlines the functi on of the self-programming library. in th is figure, a rewriting module is located in area 0 and the data in area 1 is rewritten or erased. the rewriting module is a user program to rewrite the flash memory. the other areas can also be rewritten by using the flash functions included in this self-progr amming library. the flash functions expand the entry program in the external memory or internal ram and call the device internal processing. when using the self-programming library, make sure that the hardware conditions, su ch as the write voltage, and the software conditions, such as interrupts, are satisfied. figure 16-23. functional outline of self-programming library rewriting module flash rewriting program self-programming library flash function flash environment erase/write flash memory rewriting module area 1 area 0
chapter 16 flash memory user?s manual u12768ej4v1ud 433 the configuration of the self-programming library is outlined below. figure 16-24. outline of self-p rogramming library configuration application program entry program ram parameter device internal processing flash memory self-programming interface self-programming library flash memory manipulation c interface
user?s manual u12768ej4v1ud 434 chapter 17 electrical specifications absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol conditions ratings unit v dd ?0.5 to +4.6 v v pp notes 1, 2 ?0.5 to +8.5 v av dd ?0.5 to +4.6 v bv dd ?0.5 to +4.6 v v ss ?0.5 to +0.5 v av ss ?0.5 to +0.5 v supply voltage bv ss ?0.5 to +0.5 v v i1 note 3 , p114, reset ?0.5 to v dd + 0.5 note 6 v input voltage v i2 note 4 ?0.5 to bv dd + 0.5 note 6 v clock input voltage v k x1, xt1, xt2, v dd = 2.7 to 3.6 v ?0.5 to v dd + 1.0 note 6 v analog input voltage v ian note 5 (av dd ) ?0.5 to av dd + 0.5 note 6 v analog reference input voltage av ref av ref ?0.5 to av dd + 0.5 note 6 v per pin 4.0 ma total for p00 to p07, p10 to p15, p20 to p25 25 ma total for p26, p27, p30 to p37, p100 to p107, p110 to p113 25 ma total for p40 to p47, p90 to p96, p120, clkout 25 ma output current, low i ol total for p50 to p57, p60 to p65 25 ma per pin ?4.0 ma total for p00 to p07, p10 to p15, p20 to p25 ?25 ma total for p26, p27, p30 to p37, p100 to p107, p110 to p113 ?25 ma total for p40 to p47, p90 to p96, p120, clkout ?25 ma output current, high i oh total for p50 to p57, p60 to p65 ?25 ma v o1 note 3 , v dd = 2.7 to 3.6 v ?0.5 to v dd + 0.5 note 6 v output voltage v o2 note 4 , clkout, bv dd = 2.7 to 3.6 v ?0.5 to bv dd + 0.5 note 6 v normal operating mode ?40 to +85 c 100 times guaranteed note 7 0 to 85 c operating ambient temperature t a flash memory programming mode 20 times guaranteed 10 to 40 c note 8 ? 65 to +150 c storage temperature t stg note 1 ?40 to +125 c
chapter 17 electrical specifications user?s manual u12768ej4v1ud 435 notes 1. pd70f3015b, 70f3015by, 70f3017a, and 70f3017ay only 2. make sure that the following conditions of the v pp voltage application timing are satisfied when programming flash memory. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd reached the lower-limit val ue (2.7 v) of the operating voltage range (see ?a? in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit va lue (2.7 v) of the operating voltage range of v dd (see ?b? in the figure below). 2.7 v v dd 0 v 0 v v pp 2.7 v a b notes 3. p00 to p07, p10 to p15, p20 to p27, p30 to p37, p100 to p107, p110 to p113, p120, and their alternate-function pins. 4. p40 to p47, p50 to p57, p60 to p65, p 90 to p96, and their alternate-function pins. 5. p70 to p77, p80 to p83, and their alternate-function pins. 6. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 7. the versions that guarantee 20 flas h memory rewrites can be disti nguished from the versions that guarantee 100 flash memory rewrites according to the product or the lo t number stamped on the package (xxxx indicates the four-digit num ber or symbol for internal management). ? pd70f3015b, 70f3015by: only produc ts that guarantee 100 rewrites ? pd70f3017a, 70f3017ay 20 rewrites guaranteed 100 rewrites guaranteed lot no. 0135mxxxx or earlier 0136mxxxx or later flash memory rewrite count 20 rewrites 100 rewrites flash memory rewrite temperature 10 to 40 c 0 to 85 c ? about lot no. 01 36 m4001 internal management number product week code number (example: 36th week) product year code number (example: 2001) 8. pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 703017a, and 703017ay only.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 436 cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-connector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximu m ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. capacitance (t a = 25c, v dd = av dd = bv dd = v ss = av ss = bv ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v 15 pf operating conditions (1) operating frequency, operating voltage internal operation clo ck frequency supply voltage (v dd ) 2 mhz f xx 17 mhz 2.7 to 3.6 v 2 mhz f xx 20 mhz 3.0 to 3.6 v f xt = 32.768 khz 2.7 to 3.6 v (2) cpu operating frequency parameter symbol conditions min. typ. max. unit v dd = 2.7 to 3.6 v 0.25 17 mhz operation with main clock v dd = 3.0 to 3.6 v 0.25 20 mhz cpu operating frequency f cpu operation with subclock v dd = 2.7 to 3.6 v 32.768 khz
chapter 17 electrical specifications user?s manual u12768ej4v1ud 437 recommended oscillator (1) main clock oscillator (t a = ?40 to +85c) (a) connection of ceramic res onator or crystal resonator x1 x2 parameter symbol conditions min. typ. max. unit v dd = 2.7 to 3.6 v 2 17 mhz oscillation frequency f xx v dd = 3.0 to 3.6 v 2 20 mhz upon reset release 2 19 /f xx s oscillation stabilization time upon stop mode release note s note the typ value differs depending on the setting of the osc illation stabilization time se lect register (osts). caution ensure that the duty of osc illation waveform is between 45% and 55%. remarks 1. connect the oscillator as close as possible to the x1 and x2 pins. 2. do not route the wiring near broken lines. 3. for the resonator selection and oscillator constan t, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (b) external clock input x1 x2 high-speed cmos inverter external clock open parameter symbol conditions min. typ. max. unit v dd = 2.7 to 3.6 v 2 17 mhz input frequency f xx v dd = 3.0 to 3.6 v 2 20 mhz cautions 1. connect the high-speed cmos in verter as close as possibl e to the x1 pin. 2. sufficiently evaluate the matching between the v850/sa1 and the high-speed cmos inverter.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 438 (2) subclock oscillator (t a = ?40 to +85c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt v dd = 2.7 to 3.6 v 32 32.768 35 khz oscillation stabilization time 10 s remarks 1. connect the oscillator as close as possible to the xt1 and xt2 pins. 2. do not route the wiring near broken lines. 3. for the resonator selection and oscillator constan t, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (b) external clock input parameter symbol conditions min. typ. max. unit input frequency f xt v dd = 2.7 to 3.6 v 32 32.768 35 khz cautions 1. connect the high-speed cmos in verter as close as possibl e to the xt2 pin. 2. sufficiently evaluate the matching between the v850/sa1 and the high-speed cmos inverter. xt1 xt2 high-speed cmos inverter external clock
chapter 17 electrical specifications user?s manual u12768ej4v1ud 439 dc characteristics (1) operating conditions (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 pins other than below 0.7v dd v dd v v ih2 note 1 0.7av dd av dd v v ih3 note 2 0.75v dd v dd v input voltage, high v ih4 x1, xt1 (p114), xt2 0.8v dd v dd v v il1 pins other than below v ss 0.3v dd v v il2 note 1 av ss 0.3av dd v v il3 note 2 v ss 0.2v dd v input voltage, low v il4 x1, xt1 (p114), xt2 v ss 0.2v dd v v oh1 note 3 i oh = ?3 ma 0.8v dd v output voltage, high v oh2 note 4 i oh = ?1 ma 0.8v dd v v ol1 note 3 i ol = 1.6 ma 0.4 v v ol2 note 4 (except pins p10 and p12) i ol = 1.6 ma 0.4 v output voltage, low v ol3 p10, p12 i ol = 3 ma 0.4 v v pp supply voltage note 5 v pp1 normal operation 0 0.2v dd v i lih1 pins other than below 5 a input leakage current, high i lih2 v i = v dd = av dd = bv dd x1, xt1, xt2 20 a i lil1 pins other than below ?5 a input leakage current, low i lil2 v i = 0 v x1, xt1, xt2 ?20 a output leakage current, high i loh v o = v dd = av dd = bv dd 5 a output leakage current, low i lol v o = 0 v ?5 a pull-up resistance r l v in = 0 v 10 30 100 k ? notes 1. p70 to p77, p80 to p83, and their alternate-function pins. 2. p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, reset, and their alternate-function pins. 3. clkout, p40 to p47, p50 to p57, p60 to p65, p90 to p96, p120, and thei r alternate-function pins. 4. p00 to p07, p10 to p15, p20 to p27, p30 to p37, p100 to p107, p110 to p113, and their alternate- function pins. 5. pd70f3015b, 70f3015by, 70f 3017a, 70f3017ay only.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 440 (1) operating conditions (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit i dd1 normal operation f xx = 17 mhz all peripheral functions operating 17 30 ma i dd2 halt mode f xx = 17 mhz all peripheral functions operating 8 20 ma i dd3 idle mode f xx = 17 mhz watch timer operating 1 4 ma software stop mode (subclock operation @f xt = 32.768 khz, watch timer operating) 8 60 a i dd4 software stop mode (subclock stopped (xt1 = v ss )) 1 60 a i dd5 subclock normal operation mode f xt = 32.768 khz (main clock stopped) 40 140 a pd703014a, pd703014ay, pd703014b, pd703014by, pd703015a, pd703015ay, pd703015b, pd703015by, pd703017a, pd703017ay i dd6 subclock idle mode f xt = 32.768 khz (main clock stopped, watch timer operating) 8 60 a i dd1 normal operation f xx = 17 mhz all peripheral functions operating 30 60 ma i dd2 halt mode f xx = 17 mhz all peripheral functions operating 10 25 ma i dd3 idle mode f xx = 17 mhz watch timer operating 4 8 ma software stop mode (subclock operating@f xt = 32.768 khz, watch timer operating) 10 100 a i dd4 software stop mode (subclock, stopped (xt1 = v ss )) 2 100 a i dd5 subclock normal operation mode f xt = 32.768 khz (main clock stopped) 250 600 a supply current note pd70f3015b, pd70f3015by, pd70f3017a, pd70f3017ay i dd6 subclock idle mode f xt = 32.768 khz (main clock stopped, watch timer operating) 130 360 a note the typ. value of v dd is 3.3 v. the current consumed by the output buffer is not included.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 441 (2) operating conditions (t a = ?40 to +85c, v dd = av dd = bv dd = 3.0 to 3.6 v, v ss = av ss = bv ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 pins other than below 0.7v dd v dd v v ih2 note 1 0.7av dd av dd v v ih3 note 2 0.75v dd v dd v input voltage, high v ih4 x1, xt1 (p114), xt2 0.8v dd v dd v v il1 pins other than below v ss 0.3v dd v v il2 note 1 av ss 0.3av dd v v il3 note 2 v ss 0.2v dd v input voltage, low v il4 x1, xt1 (p114), xt2 v ss 0.2v dd v v oh1 note 3 i oh = ?3 ma 0.8v dd v output voltage, high v oh2 note 4 i oh = ?1 ma 0.8v dd v v ol1 note 3 i ol = 1.6 ma 0.4 v v ol2 note 4 (except pins p10 and p12) i ol = 1.6 ma 0.4 v output voltage, low v ol3 p10, p12 i ol = 3 ma 0.4 v v pp supply voltage note 5 v pp1 normal operation 0 0.2v dd v i lih 1 pins other than below 5 a input leakage current, high i lih 2 v i = v dd = av dd = bv dd x1, xt1, xt2 20 a i lil 1 pins other than below ?5 a input leakage current, low i lil 2 v i = 0 v x1, xt1, xt2 ?20 a output leakage current, high i loh 1 v o = v dd = av dd = bv dd 5 a output leakage current, low i lol v o = 0 v ?5 a pull-up resistance r l v in = 0 v 10 30 100 k ? notes 1. p70 to p77, p80 to p83, and their alternate-function pins. 2. p00 to p07, p10, p12, p 13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, reset and their alternate-function pins. 3. clkout, p40 to p47, p50 to p57, p60 to p65, p90 to p96, p120, and thei r alternate-function pins. 4. p00 to p07, p10 to p15, p20 to p27, p30 to p37, p100 to p107, p110 to p113, and their alternate- function pins. 5. pd70f3015b, 70f3015by, 70f 3017a, 70f3017ay only.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 442 (2) operating conditions (t a = ?40 to +85c, v dd = av dd = bv dd = 3.0 to 3.6 v, v ss = av ss = bv ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit i dd1 normal operation f xx = 20 mhz all peripheral functions operating 20 35 ma i dd2 halt mode f xx = 20 mhz all peripheral functions operating 9 22 ma i dd3 idle mode f xx = 20 mhz watch timer operating 1.2 4.5 ma software stop mode (subclock operation @f xt = 32.768 khz, watch timer operating) 8 60 a i dd4 software stop mode (subclock stopped (xt1 = v ss )) 1 60 a i dd5 subclock normal operation mode f xt = 32.768 khz (main clock stopped) 40 140 a pd703014a, pd703014ay, pd703014b, pd703014by, pd703015a, pd703015ay, pd703015b, pd703015by, pd703017a, pd703017ay i dd6 subclock idle mode f xt = 32.768 khz (main clock stopped, watch timer operating) 8 60 a i dd1 normal operation f xx = 20 mhz all peripheral functions operating 32 64 ma i dd2 halt mode f xx = 20 mhz all peripheral functions operating 11 26 ma i dd3 idle mode f xx = 20 mhz watch timer operating 4.5 9 ma software stop mode (subclock operating@f xt = 32.768 khz, watch timer operating) 10 100 a i dd4 software stop mode (subclock stopped (xt1 = v ss )) 2 100 a i dd5 subclock normal operation mode f xt = 32.768 khz (main clock stopped) 250 600 a supply current note 5 pd70f3015b, pd70f3015by, pd70f3017a, pd70f3017ay i dd6 subclock idle mode f xt = 32.768 khz (main clock stopped, watch timer operating) 130 360 a note the typ. value of v dd is 3.3 v. the current consumed by the output buffer is not included.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 443 data retention characteristics (t a = ?40 to +85c, v ss = av ss = bv ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.8 3.6 v note 1 1 60 a data retention current i dddr v dd = v dddr , xt1 = v ss note 2 2 100 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage hold time (from stop mode setting) t hvd 0 ms stop mode release signal input time t drel 0 ms data retention high-level input voltage v ihdr all input ports v ihn v dddr v data retention low-level input voltage v ildr all input ports 0 v iln v notes 1. pd703014a, 703014ay, 703014b, 703014by, 703015a, 703015ay, 703015b, 703015by, 703017a, 703017ay only 2. pd70f3015b, 70f3015by, 70f3017a, 70f3017ay only remarks 1. typ. values are reference values for when t a = 25c. 2. n = 1 to 4 note v dd = 2.7 v indicates the minimum oper ating voltage of the v850/sa1 (when f xx = 17 mhz). caution shifting to stop mode and restoring from stop m ode must be performed at v dd = 2.7 v min. (f xx = 17 mhz) and v dd = 3.0 v min. (f xx = 20 mhz), respectively. v dd 2.7 v note setting stop mode t hvd t fvd reset (input) stop mode release interrupt (nmi, etc.) (when stop mode is released at falling edge) stop mode release interrupt (nmi, etc.) (when stop mode is released at rising edge) t rvd t drel v dddr v ihdr v ildr v ihdr
chapter 17 electrical specifications user?s manual u12768ej4v1ud 444 ac characteristics ac test input measurement points (1) p11, p14, p21, p24, p34, p35, p40 to p47, p50 to p 57, p60 to p65, p90 to p96, p100 to p107, p110 to p113, p120, and their alternate-function pins v dd 0 v 0.7v dd 0.3v dd 0.7v dd 0.3v dd point of measurement (2) p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, reset, and their alternate-function pins v dd 0 v 0.75v dd 0.2v dd 0.75v dd 0.2v dd point of measurement (3) x1, xt1 (p114), xt2 v dd 0 v 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement ac test output measurement points load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit c onfiguration, bring the load capacitance of the device to 50 pf or less by inserting a buffe r or by some other means. 0.8v dd 0.4 v 0.8v dd 0.4 v point of measurement v dd 0 v
chapter 17 electrical specifications user?s manual u12768ej4v1ud 445 clock timing (1) operating conditions (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit x1 input cycle 58.8 500 ns xt1 input cycle t cyx <1> 28.5 31.2 s x1 input high-level width 26.4 ns xt1 input high-level width t wxh <2> 12.8 s x1 input low-level width 26.4 ns xt1 input low-level width t wxl <3> 12.8 s x1, xt1 input rise time t xr <4> 0.5 (t cyx ? t wxh ? t wxl ) ns x1, xt1 input fall time t xf <5> 0.5 (t cyx ? t wxh ? t wxl ) ns clkout output cycle t cyk <6> 58.8 ns 31.2 s clkout high-level width t wkh <7> 0.4t cyk ? 10 ns clkout low-level width t wkl <8> 0.4t cyk ? 10 ns clkout rise time t kr <9> 10 ns clkout fall time t kf <10> 10 ns remark ensure that the duty is between 45% and 55%. (2) operating conditions (t a = ?40 to +85c, v dd = av dd = bv dd = 3.0 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit x1 input cycle 50.0 500 ns xt1 input cycle t cyx <1> 28.5 31.2 s x1 input high-level width 22.5 ns xt1 input high-level width t wxh <2> 12.8 s x1 input low-level width 22.5 ns xt1 input low-level width t wxl <3> 12.8 s x1, xt1 input rise time t xr <4> 0.5 (t cyx ? t wxh ? t wxl ) ns x1, xt1 input fall time t xf <5> 0.5 (t cyx ? t wxh ? t wxl ) ns clkout output cycle t cyk <6> 50.0 ns 31.2 s clkout high-level width t wkh <7> 0.4t cyk ? 10 ns clkout low-level width t wkl <8> 0.4t cyk ? 10 ns clkout rise time t kr <9> 10 ns clkout fall time t kf <10> 10 ns remark ensure that the duty is between 45% and 55%.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 446 clock timing x1, xt1 (input) clkout (output) <2> <4> <5> <1> <3> <7> <9> <10> <8> <6> timing of pins other than clkout, ports 4, 5, 6, and 9 (t a = ?40 to +85 c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output rise time t or <11> 20 ns output fall time t of <12> 20 ns output signal <11> <12>
chapter 17 electrical specifications user?s manual u12768ej4v1ud 447 bus timing (clkout asynchronous) (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <13> 0.5t ? 15 ns address hold time (from astb ) t hsta <14> 0.5t ? 15 ns address float delay time from dstb t fda <15> 2 ns data input setup time from address t said <16> (2 + n)t ? 25 ns data input setup time from dstb t sdid <17> (1 + n)t ? 25 ns delay time from astb to dstb t dstd <18> 0.5t ? 15 ns data input hold time (from dstb ) t hdid <19> 0 ns address output time from dstb t dda <20> (1 + i)t ? 15 ns delay time from dstb to astb t ddst1 <21> 0.5t ? 15 ns delay time from dstb to astb t ddst2 <22> (1.5 + i)t ? 15 ns dstb low-level width t wdl <23> (1 + n)t ? 15 ns astb high-level width t wsth <24> t ? 15 ns data output time from dstb t ddod <25> 15 ns data output setup time (to dstb ) t sodd <26> (1 + n)t ? 20 ns data output hold time (from dstb ) t hdod <27> t ? 15 ns t sawt1 <28> n 1 1.5t ? 25 ns wait setup time (to address) t sawt2 <29> n 1 (1.5 + n)t ? 25 ns t hawt1 <30> n 1 (0.5 + n)t ns wait hold time (from address) t hawt2 <31> n 1 (1.5 + n)t ns t sstwt1 <32> n 1 t ? 25 ns wait setup time (to astb ) t sstwt2 <33> n 1 (1 + n)t ? 25 ns t hstwt1 <34> n 1 nt ns wait hold time (from astb ) t hstwt2 <35> n 1 (1 + n)t ns hldrq high-level width t whqh <36> t + 10 ns hldak low-level width t whal <37> t ? 15 ns bus output delay time from hldak t dhac <38> 0 ns delay time from hldrq to hldak t dhqha1 <39> (2n + 7.5)t + 25 ns delay time from hldrq to hldak t dhqha2 <40> 0.5t 1.5t + 25 ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle states inse rted after the read cycle (0 or 1). 4. the values in the above specificat ions are values for when clocks wit h a 1:1 duty ratio are input from x1.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 448 bus timing (clkout synchronous) (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <41> 0 19 ns delay time from clkout to address float t fka <42> ?12 7 ns delay time from clkout to astb t dkst <43> ?12 7 ns delay time from clkout to dstb t dkd <44> ?5 14 ns data input setup time (to clkout ) t sidk <45> 15 ns data input hold time (from clkout ) t hkid <46> 5 ns data output delay time from clkout t dkod <47> 19 ns wait setup time (to clkout ) t swtk <48> 15 ns wait hold time (from clkout ) t hkwt <49> 5 ns hldrq setup time (to clkout ) t shqk <50> 15 ns hldrq hold time (from clkout ) t hkhq <51> 5 ns delay time from clkout to bus float t dkf <52> 19 ns delay time from clkout to hldak t dkha <53> 19 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 449 read cycle (clkout sync hronous/asynchronous, 1 wait) clkout (output) a16 to a21 (output), a1 to a15 (output), note ad0 to ad15 (i/o) astb (output) dstb (output), rd (output) wait (input) t1 t2 tw t3 <41> <42> <43> <13> <44> <21> <20> <22> <18> <32> <48> <34> <33> <35> <28> <30> <29> <31> <49> <48> <49> <17> <23> <19> <43> <16> <45> <46> address hi-z <15> <44> <14> <24> note r/w (output), uben (output), lben (output) remark wrl and wrh are high level. data
chapter 17 electrical specifications user?s manual u12768ej4v1ud 450 write cycle (clkout sync hronous/asynchronous, 1 wait) clkout (output) a16 to a21 (output), a1 to a15 (output), note ad0 to ad15 (i/o) astb (output) dstb (output), wrl (output), wrh (output) wait (input) t1 t2 tw t3 <41> <47> <43> <13> <44> <21> <27> <18> <32> <48> <34> <33> <35> <28> <30> <29> <31> <49> <48> <49> <26> <23> <24> <14> <43> data address <25> <44> note r/w (output), uben (output), lben (output) remark rd is high level.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 451 bus hold clkout (output) hldrq (input) hldak (output) a16 to a19 (output), note a1 to a15 (output) ad0 to ad15 (i/o) astb (output) dstb (output), rd (output), wrl (output), wrh (output) <50> <51> <53> <38> <37> <39> <40> <50> <53> <36> th th th ti hi-z hi-z hi-z data hi-z note r/w (output), uben (output), lben (output) <52>
chapter 17 electrical specifications user?s manual u12768ej4v1ud 452 reset/interrupt timing (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit reset high-level width t wrsh <54> 500 ns reset low-level width t wrsl <55> 500 ns nmi high-level width t wnih <56> 500 ns nmi low-level width t wnil <57> 500 ns n = 0 to 3 (analog noise elimination) 500 ns intpn high-level width t with <58> n = 4 to 6 (digital noise elimination) 3t + 20 ns n = 0 to 3 (analog noise elimination) 500 ns intpn low-level width t witl <59> n = 4 to 6 (digital noise elimination) 3t + 20 ns remark t = 1/f xx reset <54> <55> reset (input) interrupt <56> <57> nmi (input) <58> <59> intpn (input) remark n = 0 to 6
chapter 17 electrical specifications user?s manual u12768ej4v1ud 453 tin input timing (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit tin0, tin1 high-level width n = 0, 1 2t sam + 20 note ns tin high-level width t tihn <60> n = 2 to 5 3t + 20 ns tin0, tin1 low-level width n = 0, 1 2t sam + 20 note ns tin low-level width t tiln <61> n = 2 to 5 3t + 20 ns note t sam (count clock cycle) can be selected as follows by setting the prmn2 to prmn0 bits of prescaler mode register n, n1 (prmn, prmn1). when n = 0 (tm0): t sam = 2t, 4t, 16t, 64t, 256t or 1/intwti cycle when n = 1 (tm1): t sam = 2t, 4t, 16t, 32t, 128t, or 256t cycle however, when the tin0 valid edge is selected as the count clock, t sam = 2t. remark t= 1/f xx <60> <61> tln remark n = 00, 01, 10, 11, 2 to 5
chapter 17 electrical specifications user?s manual u12768ej4v1ud 454 csi timing (1) master mode (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy1 <62> 400 ns sckn high-/low-level width t kh1 , t kl1 <63> 140 ns sin setup time (to sckn ) t sik1 <64> 50 ns sin hold time (from sckn ) t ksi1 <65> 50 ns delay time from sckn to son output t kso1 <66> 60 ns remark n = 0 to 2 (2) slave mode (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy2 <62> 400 ns sckn high-/low-level width t kh2 , t kl2 <63> 140 ns sin setup time (to sckn ) t sik2 <64> 50 ns sin hold time (from sckn ) t ksi2 <65> 50 ns delay time from sckn to son output t kso2 <66> 60 ns remark n = 0 to 2 <65> <66> <64> <62> <63> <63> remark n = 0 to 2 sckn (i/o) sin (input) son (output) input data output data hi-z hi-z
chapter 17 electrical specifications user?s manual u12768ej4v1ud 455 uart timing (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit asckn cycle time t kcy13 <67> 200 ns asckn high-level width t kh13 <68> 80 ns asckn low-level width t kl13 <69> 80 ns remark n = 0 or 1 <68> <69> <67> asckn (input) remark n = 0 or 1
chapter 17 electrical specifications user?s manual u12768ej4v1ud 456 i 2 c bus mode ( pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, 70f3017ay only) (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, c l = 50 pf) normal mode high-speed mode parameter symbol min. max. min. max. unit scl clock frequency f clk 0 100 0 400 khz bus-free time (between stop/start conditions) t buf <70> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <71> 4.0 ? 0.6 ? s scl clock low-level width t low <72> 4.7 ? 1.3 ? s scl clock high-level width t high <73> 4.0 ? 0.6 ? s setup time for start/restart condition t su:sta <74> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <75> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <76> 250 ? 100 note 4 ? ns sda and scl signal rise time t r <77> ? 1000 20 + 0.1cb note 5 300 ns sda and scl signal fall time t f <78> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <79> 4.0 ? 0.6 ? s width of spike pulse suppressed by input filter t sp <80> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clo ck pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time inte rnally for the sda signal in order to occupy the undefined area at the falling edge of scl. 3. if the system does not extend t he scl signal low hold time (t low ), only the maximum data hold time (t hd:dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl signal's low state hold time: t su:dat 250 ns ? if the system extends the scl signal's low state hold time: transmit the following data bit to the sda line prior to the scl line release (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark the maximum operating frequency of the pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, and pd70f3017ay is f xx = 17 mhz.
chapter 17 electrical specifications user?s manual u12768ej4v1ud 457 i 2 c bus mode ( pd703014ay, 703014by, 703015ay, 703015by, 703017ay, 70f3015by, 70f3017ay only) a/d converter (t a = ?40 to +85c, v dd = av dd = av ref = 2.7 to 3.6 v, av ss = v ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 0.8 %fsr conversion time t conv 5 100 s zero-scale error note 1 0.4 %fsr full-scale error note 1 0.4 %fsr integral linearity error note 2 4 lsb differential linearity error note 2 4 lsb analog reference voltage av ref av ref = av dd 2.7 3.6 v analog input voltage v ian av ss av ref v av ref current ai ref 360 500 a av dd power supply current ai dd 1 3 ma notes 1. excluding quantization error ( 0.05% fsr). 2. excluding quantization error ( 0.5 lsb) remark fsr: full scale range lsb: least significant bit stop condition start condition restart condition stop condition scl (i/o) sda (i/o) <71> <70> <72> <73 <77> <77> <78> <78> <75> <76> <74> <71> <79> <80>
chapter 17 electrical specifications user?s manual u12768ej4v1ud 458 flash memory programming mode ( pd70f3015b, 70f3015by, 70f 3017a, 70f3017ay only) write/erase characteristics (t a = 0 to 85 c, v dd = av dd = bv dd = 3.0 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 7.5 7.8 8.1 v v dd supply current i dd when v pp = v pp2 , f xx = 20 mhz 67 ma v pp supply current i pp v pp = v pp2 , 0.1 s after erasure 100 ma step erase time t er note 1 0.2 s overall erase time per area note 2 t era when step erase time = 0.2 s, note 3 20 s/area write-back time t wb note 4 1 ms number of write-backs per write-back command c wb when write-back time = 1 ms, note 5 300 c ount/write- back command number of erase/write-backs c erwb 16 count step writing time t wr note 6 20 s overall writing time per word t wrw when step writing time = 20 s (1 word = 4 bytes), note 7 20 200 s/word 100 c ount/area number of rewrites per area note 2 c erwr 1 erase + 1 write after erase = 1 rewrite, notes 8, 9 20 count/area notes 1. the recommended setting value of t he step erase time is 0.2 s. 2. no areas are included in the pd70f3015b and 70f3015by. the areas the pd70f3017a and 70f3017ay are as follows. area 0 = 000000h to 01ffffh area 1 = 020000h to 03ffffh 3. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 4. the recommended setting value of the write-back time is 1 ms. 5. write-back is executed once by t he issuance of the write-back comm and. therefore, the retry count must be the maximum value minus the number of commands issued. 6. the recommended setting value of the step writing time is 20 s. 7. 20 s is added to the actual writing time per word. the in ternal verify time during and after the writing is not included. 8. when writing initially to shipped produc ts, it is counted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites
chapter 17 electrical specifications user?s manual u12768ej4v1ud 459 notes 9. the versions that guarantee 20 rewrites can be distinguished from the versions that guarantee 100 rewrites according to the product or the lo t number stamped on the package (xxxx indicates the four-digit number or symbol for internal management). ? pd70f3015b,70f3015by: only products that guarantee 100 rewrites (rewrite temperature: 0 to 85 c) ? pd70f3017a, 70f3017ay 20 rewrites guaranteed 100 rewrites guaranteed lot no. 0135mxxxx or earlier 0136mxxxx or later flash memory rewrite count 20 rewrites 100 rewrites flash memory rewrite temperature 10 to 40 c 0 to 85 c ? about lot no. 01 36 m4001 internal management number product week code number (example: 36th week) product year code number (example: 2001) remark when the pg-fp3 and pg-fp4 are used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings unless otherwise specified.
user?s manual u12768ej4v1ud 460 chapter 18 package drawings 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
chapter 18 package drawings user?s manual u12768ej4v1ud 461 121-pin plastic fbga (12x12) item millimeters d 12.00 0.10 e 12.00 0.10 0.10 p121f1-80-ea6 index mark a w 0.20 a2 a1 a 1.13 e 0.80 1.48 0.10 0.35 0.06 x y 0.20 y1 1.20 zd 1.20 ze 0.08 ze a2 a1 b zd b a s s wa s wb s y1 se y 13 12 11 10 9 8 7 6 5 4 3 2 1 nmlk jhgfedcba s xab m e d b 0.50 + 0.05 ? 0.10
user?s manual u12768ej4v1ud 462 chapter 19 recommended soldering conditions the v850/sa1 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, consult an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) table 19-1. surface mounting type soldering conditions (1/4) (1) pd703014bgc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703014bygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703015bgc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703015bygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less ir35-00-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: two times or less vp15-00-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering met hods together (except for partial heating). (2) pd703017agc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703017aygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3015bgc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3015bygc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125c for 10 hours) ir35-107-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125c for 10 hours) vp15-107-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating).
chapter 19 recommended soldering conditions user?s manual u12768ej4v1ud 463 table 19-1. surface mounting ty pe soldering conditions (2/4) (3) pd70f3017agc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3017aygc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less exposure limit: 3 days note (after that, prebake at 125c for 10 hours) ir35-103-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: two times or less exposure limit: 3 days note (after that, prebake at 125c for 10 hours) vp15-103-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). (4) pd703014af1- -ea6: 121-pin plastic fbga (12 12) pd703014ayf1- -ea6: 121-pin plastic fbga (12 12) pd703015af1- -ea6: 121-pin plastic fbga (12 12) pd703015ayf1- -ea6: 121-pin plastic fbga (12 12) pd703017af1- -ea6: 121-pin plastic fbga (12 12) pd703017ayf1- -ea6: 121-pin plastic fbga (12 12) pd70f3017af1-ea6: 121-pin plastic fbga (12 12) pd70f3017ayf1-ea6: 121-pin plastic fbga (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 hours) ir35-107-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 hours) vp15-107-2 note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating).
chapter 19 recommended soldering conditions user?s manual u12768ej4v1ud 464 table 19-1. surface mounting ty pe soldering conditions (3/4) (5) pd703015bgc-xxx-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd703015bygc-xxx-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd703017aygc-xxx-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3015bgc-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3017agc-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125c for 20 to 72 hours) ir60-203-3 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). remark products with -a at the end of t he part number are lead-free products. (6) pd703014bgc-xxx-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd703014bygc-xxx-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd703017agc-xxx-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3015bygc-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3017aygc-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). remark products with -a at the end of t he part number are lead-free products.
chapter 19 recommended soldering conditions user?s manual u12768ej4v1ud 465 table 19-1. surface mounting ty pe soldering conditions (4/4) (7) pd703014af1- -ea6-a: 121-pin plastic fbga (12 12) pd703014ayf1- -ea6-a: 121-pin plastic fbga (12 12) pd703014bf1- -ea6-a: 121-pin plastic fbga (12 12) pd703015af1- -ea6-a: 121-pin plastic fbga (12 12) pd703015ayf1- -ea6-a: 121-pin plastic fbga (12 12) pd703015bf1- -ea6-a: 121-pin plastic fbga (12 12) pd703017af1- -ea6-a: 121-pin plastic fbga (12 12) pd703017ayf1- -ea6-a: 121-pin plastic fbga (12 12) pd70f3015bf1-ea6-a: 121-pin plastic fbga (12 12) pd70f3017af1-ea6-a: 121-pin plastic fbga (12 12) pd70f3017ayf1-ea6-a: 121-pin plastic fbga (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125c for 20 to 72 hours) ir60-203-3 note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). remark products with -a at the end of t he part number are lead-free products. (8) pd703014byf1- -ea6-a: 121-pin plastic fbga (12 12) pd703015byf1- -ea6-a: 121-pin plastic fbga (12 12) pd70f3015byf1-ea6-a: 121-pin plastic fbga (12 12) undefined
user?s manual u12768ej4v1ud 466 appendix a notes on target system design the following shows a diagram of t he connection conditions between the in -circuit emulator option board and conversion connector. design your system making allowanc es for conditions such as the shape of parts mounted on the target system as shown below. figure a-1. 100-pin plastic lqfp (fine pitch) (14 14) side view target system nqpack100sd yqpack100sd 167 mm note in-circuit emulator option board conversion connector ie-703017-mc-em1 in-circuit emulator ie-703002-mc yqguide note yqsocket100sdn (included with ie -703002-mc) can be inserted here to adjust the height (height: 3.2 mm). top view target system yqpack100sd, nqpack100sd, yqguide ie-703017-mc-em1 ie-703002-mc pin 1 position connection condition diagram 13.3 mm 23.4 mm 22.13 mm 15.24 mm 75 mm 30.74 mm target system nqpack100sd yqpack100sd ie-703017-mc-em1 connect to ie-703002-mc. yqguide pin 1 position
appendix a notes on target system design user?s manual u12768ej4v1ud 467 figure a-2. 121-pin plastic fbga (12 12) side view target system 167 mm in-circuit emulator option board conversion adapter ie-703017-mc-em1 in-circuit emulator ie-703002-mc csice121a1312n02 cspack121a1312n02 top view target system cspack121a1312n02, csice121a1312n02 ie-703017-mc-em1 ie-703002-mc pin 1 position connection condition diagram 11.1 mm 23.4 mm 22.13 mm 15.24 mm 75 mm 30.74 mm target system csice121a1312n02 cspack121a1312n02 ie-703017-mc-em1 connect to ie-703002-mc pin 1 position
user?s manual u12768ej4v1ud 468 appendix b register index (1/5) symbol name unit page adcr a/d conversion result register adc 310 adcrh a/d conversion result register h adc 310 adic interrupt control register intc 122 to 124 adm a/d converter mode register adc 312 ads analog input channel spec ification register adc 315 asim0 asynchronous serial interface mode register 0 uart 288 asim1 asynchronous serial interface mode register 1 uart 288 asis0 asynchronous serial interf ace status register 0 uart 290 asis1 asynchronous serial interf ace status register 1 uart 290 bcc bus cycle control register bcu 95 brgc0 baud rate generator control register 0 brg 291 brgc1 baud rate generator control register 1 brg 291 brgmc0 baud rate generator mode control register 0 brg 292 brgmc01 baud rate generator mode control register 01 brg 292 brgmc1 baud rate generator mode control register 1 brg 293 cr00 capture/compare register 00 rpu 156 cr01 capture/compare register 01 rpu 157 cr10 capture/compare register 10 rpu 156 cr11 capture/compare register 11 rpu 157 cr20 8-bit compare register 2 rpu 191 cr23 16-bit compare register 23 (when tm2 and tm3 are connected in cascade) rpu 205 cr30 8-bit compare register 3 rpu 191 cr40 8-bit compare register 4 rpu 191 cr45 16-bit compare register 45 (when tm4 and tm5 are connected in cascade) rpu 205 cr50 8-bit compare register 5 rpu 191 crc0 capture/compare control register 0 rpu 160 crc1 capture/compare control register 1 rpu 160 csic0 interrupt control register intc 122 to 124 csic1 interrupt control register intc 122 to 124 csic2 interrupt control register intc 122 to 124 csim0 serial operation mode register 0 csi 223 csim1 serial operation mode register 1 csi 223 csim2 serial operation mode register 2 csi 223
appendix b register index user?s manual u12768ej4v1ud 469 (2/5) symbol name unit page csis0 serial clock sele ct register 0 csi 223 csis1 serial clock sele ct register 1 csi 223 csis2 serial clock sele ct register 2 csi 223 dbc0 dma byte counter register 0 dmac 335 dbc1 dma byte counter register 1 dmac 335 dbc2 dma byte counter register 2 dmac 335 dchc0 dma channel control register 0 dmac 336 dchc1 dma channel control register 1 dmac 336 dchc2 dma channel control register 2 dmac 336 dioa0 dma peripheral i/o address register 0 dmac 332 dioa1 dma peripheral i/o address register 1 dmac 332 dioa2 dma peripheral i/o address register 2 dmac 332 dmaic0 interrupt control register intc 122 to 124 dmaic1 interrupt control register intc 122 to 124 dmaic2 interrupt control register intc 122 to 124 dra0 dma internal ram address register 0 dmac 332 dra1 dma internal ram address register 1 dmac 332 dra2 dma internal ram address register 2 dmac 332 dwc data wait control register bcu 93 ecr interrupt source register cpu 62 egn0 falling edge specificati on register intc 114, 351 egp0 rising edge specificati on register intc 114, 351 eipc interrupt status saving register cpu 62 eipsw interrupt status saving register cpu 62 fepc nmi status saving register cpu 62 fepsw nmi status saving register cpu 62 flpmc flash memory programming mode control register cpu 423 iic0 iic shift register 0 i 2 c 242 iicc0 iic control register 0 i 2 c 234 iiccl0 iic clock select register 0 i 2 c 241 iics0 iic status register 0 i 2 c 238 iicx0 iic function expansion register 0 i 2 c 241 ispr in-service priority register intc 125 mam memory address output mode register port 78 mm memory expansion mode register port 77 osts oscillation stabilization time select register wdt 143, 215, 220 p0 port 0 port 348 p1 port 1 port 353
appendix b register index user?s manual u12768ej4v1ud 470 (3/5) symbol name unit page p10 port 10 port 383 p11 port 11 port 387 p12 port 12 port 390 p2 port 2 port 359 p3 port 3 port 367 p4 port 4 port 372 p5 port 5 port 372 p6 port 6 port 375 p7 port 7 port 377 p8 port 8 port 377 p9 port 9 port 379 pcc processor clock control register cg 140 pf1 port 1 function register port 355 pf10 port 10 function register port 385 pf2 port 2 function register port 361 pic0 interrupt control register intc 122 to 124 pic1 interrupt control register intc 122 to 124 pic2 interrupt control register intc 122 to 124 pic3 interrupt control register intc 122 to 124 pic4 interrupt control register intc 122 to 124 pic5 interrupt control register intc 122 to 124 pic6 interrupt control register intc 122 to 124 pm0 port 0 mode register port 350 pm1 port 1 mode register port 354 pm10 port 10 mode register port 384 pm11 port 11 mode register port 388 pm12 port 12 mode register port 391 pm2 port 2 mode register port 360 pm3 port 3 mode register port 368 pm4 port 4 mode register port 373 pm5 port 5 mode register port 373 pm6 port 6 mode register port 376 pm9 port 9 mode register port 380 pmc12 port 12 mode control register port 391 prcmd command register cg 88 prm0 prescaler mode register 0 rpu 162 prm01 prescaler mode register 01 rpu 162
appendix b register index user?s manual u12768ej4v1ud 471 (4/5) symbol name unit page prm1 prescaler mode register 1 rpu 164 prm11 prescaler mode register 11 rpu 164 psc power save control register cg 142 psw program status word cpu 63 pu0 pull-up resistor option register 0 port 350 pu1 pull-up resistor option register 1 port 355 pu10 pull-up resistor option register 10 port 385 pu11 pull-up resistor option register 11 port 388 pu2 pull-up resistor option register 2 port 361 pu3 pull-up resistor option register 3 port 368 rtbh real-time output buffer register h rpu 342 rtbl real-time output buffer register l rpu 342 rtpc real-time output port control register rpu 344 rtpm real-time output port mode register rpu 343 rx0 receive shift register 0 uart 287 rx1 receive shift register 1 uart 287 rxb0 receive buffer register 0 uart 287 rxb1 receive buffer register 1 uart 287 sar successive approximation register adc 310 seric0 interrupt control register intc 122 to 124 seric1 interrupt control register intc 122 to 124 sio0 serial i/o shift register 0 csi 222 sio1 serial i/o shift register 1 csi 222 sio2 serial i/o shift register 2 csi 222 sric1 interrupt control register intc 122 to 124 stic0 interrupt control register intc 122 to 124 stic1 interrupt control register intc 122 to 124 sva0 slave address register 0 i 2 c 242 syc system control register bcu 90 sys system status register cg 88 tcl2 timer clock select register 2 rpu 193 tcl21 timer clock select register 21 rpu 193 tcl3 timer clock select register 3 rpu 193 tcl31 timer clock select register 31 rpu 193 tcl4 timer clock select register 4 rpu 193 tcl41 timer clock select register 41 rpu 193 tcl5 timer clock select register 5 rpu 193
appendix b register index user?s manual u12768ej4v1ud 472 (5/5) symbol name unit page tcl51 timer clock select register 51 rpu 193 tm0 16-bit timer register 0 rpu 155 tm1 16-bit timer register 1 rpu 155 tm2 8-bit counter 2 rpu 191 tm23 16-bit counter 23 (when tm2 and tm 3 are connected in cascade) rpu 205 tm3 8-bit counter 3 rpu 191 tm4 8-bit counter 4 rpu 191 tm45 16-bit counter 45 (when tm4 and tm 5 are connected in cascade) rpu 205 tm5 8-bit counter 5 rpu 191 tmc0 16-bit timer mode control register 0 rpu 158 tmc1 16-bit timer mode control register 1 rpu 158 tmc2 8-bit timer mode control register 2 rpu 195 tmc3 8-bit timer mode control register 3 rpu 195 tmc4 8-bit timer mode control register 4 rpu 195 tmc5 8-bit timer mode control register 5 rpu 195 tmic00 interrupt control register intc 122 to 124 tmic01 interrupt control register intc 122 to 124 tmic10 interrupt control register intc 122 to 124 tmic11 interrupt control register intc 122 to 124 tmic2 interrupt control register intc 122 to 124 tmic3 interrupt control register intc 122 to 124 tmic4 interrupt control register intc 122 to 124 tmic5 interrupt control register intc 122 to 124 toc0 16-bit timer output control register 0 rpu 161 toc1 16-bit timer output control register 1 rpu 161 txs0 transmit shift register 0 uart 287 txs1 transmit shift register 1 uart 287 wdcs watchdog timer clock select register wdt 216 wdtic interrupt control register intc 122 to 124 wdtm watchdog timer mode register wdt 126, 217 wtic interrupt control register intc 122 to 124 wtiic interrupt control register intc 122 to 124 wtm watch timer mode control register wt 210
user?s manual u12768ej4v1ud 473 appendix c list of instruction sets ? how to read instruction set list mnemonic operand opcode operation flag cy ov s z sat this column shows the instruction group. instructions are divided into each instruction group and described. this column shows the instruction mnemonic. this column shows the instruction operand (refer to table c-1 ). this column shows the instruction operation (refer to table c-3 ). this column shows the flag status (refer to table c-4 ). this column shows the instruction code (opcode) in binary format. 32-bit instructions are displayed in 2 lines (refer to table c-2 ). instruction group table c-1. symbols in operand description symbol description reg1 general-purpose register (r0 to r31): used as source register reg2 general-purpose register (r0 to r31): mainly us ed as destination register ep element pointer (r30) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement regid system register number vector 5-bit data that specifies trap vector number (00h to 1fh) cccc 4-bit data that indicates condition code
appendix c list of instruction sets user?s manual u12768ej4v1ud 474 table c-2. symbols used for opcode symbol description r 1-bit data of code that specifies reg1 or regid r 1-bit data of code that specifies reg2 d 1-bit data of displacement i 1-bit data of immediate data cccc 4-bit data that indicates condition code bbb 3-bit data that specifies bit number table c-3. symbols used for operation description symbol description assignment gr[ ] general-purpose register sr[ ] system register zero-extend (n) zero-extends n to word length. sign-extend (n) sign-extends n to word length. load-memory (a,b) reads data of size b from address a. store-memory (a,b,c) writes data b of size c to address a. load-memory-bit (a,b) reads bit b from address a. store-memory-bit (a,b,c) writes c to bit b of address a. saturated (n) performs saturated proce ssing of n. (n is 2?s complement). result of calculation of n: if n is n 7fffffffh as result of calculation, 7fffffffh. if n is n 80000000h as result of calculation, 80000000h. result reflects result to a flag. byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + add ? subtract || bit concatenation multiply divide and logical product or logical sum xor exclusive logical sum not logical negate logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift
appendix c list of instruction sets user?s manual u12768ej4v1ud 475 table c-4. symbols used for flag operation symbol description (blank) not affected 0 cleared to 0 set or cleared according to result r previously saved value is restored table c-5. condition codes condition name (cond) condition code (cccc) conditional expression description v 0000 ov = 1 overflow nv 1000 ov = 0 no overflow c/l 0001 cy = 1 carry lower (less than) nc/nl 1001 cy = 0 no carry no lower (greater than or equal) z/e 0010 z = 1 zero equal nz/ne 1010 z = 0 not zero not equal nh 0011 (cy or z) = 1 not higher (less than or equal) h 1011 (cy or z) = 0 higher (greater than) n 0100 s = 1 negative p 1100 s = 0 positive t 0101 ? always (unconditional) sa 1101 sat = 1 saturated lt 0110 (s xor ov) = 1 less than signed ge 1110 (s xor ov) = 0 greater than or equal signed le 0111 ( (s xor ov) or z) = 1 less than or equal signed gt 1111 ( (s xor ov) or z) = 0 greater than signed
appendix c list of instruction sets user?s manual u12768ej4v1ud 476 instruction set list (1/4) flag instruction group mnemonic operand opcode operation cy ov s z sa t sld.b disp7 [ep], reg2 rrrrr0110ddddddd adr ep + zero-extend (disp7) gr [reg2] sign-extend (load-memory (adr, byte)) sld.h disp8 [ep], reg2 rrrrr1000ddddddd note 1 adr ep + zero-extend (disp8) gr [reg2] sign-extend (load-memory (adr, halfword)) sld.w disp8 [ep], reg2 rrrrr1010dddddd0 note 2 adr ep + zero-extend (disp8) gr [reg2] load-memory (adr, word) ld.b disp16 [reg1], reg2 rrrrr111000rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, byte)) ld.h disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd0 note 3 adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, halfword)) ld.w disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd1 note 3 adr gr [reg1] + sign-extend (disp16) gr [reg2] load-memory (adr, word)) sst.b reg2, disp7 [ep] rrrrr0111ddddddd adr ep + zero-extend (disp7) store-memory (adr, gr [reg2], byte) sst.h reg2, disp8 [ep] rrrrr1001ddddddd note 1 adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], halfword) sst.w reg2, disp8 [ep] rrrrr1010dddddd1 note 2 adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], word) st.b reg2, disp16 [reg1] rrrrr111010rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], byte) st.h reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd0 note 3 adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], halfword) load/store st.w reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd1 note 3 adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], word) mov reg1, reg2 rrrrr000000rrrrr gr [reg2] gr [reg1] mov imm5, reg2 rrrrr010000iiiii gr [reg2] sign-extend (imm5) movhi imm16, reg1, reg2 rrrrr110010rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + (imm16 || 0 16 ) arithmetic operation movea imm16, reg1, reg2 rrrrr110001rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) notes 1. ddddddd is the higher 7 bits of disp8. 2. dddddd is the higher 6 bits of disp8. 3. ddddddddddddddd is the higher 15 bits of disp16.
appendix c list of instruction sets user?s manual u12768ej4v1ud 477 instruction set list (2/4) flag instruction group mnemonic operand opcode operation cy ov s z sa t add reg1, reg2 rrrrr001110rrrrr gr [reg2] gr [reg2] + gr [reg1] add imm5, reg2 rrrrr010010iiiii gr [reg2] gr [reg2] + sign-extend (imm5) addi imm16, reg1, reg2 rrrrr110000rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) sub reg1, reg2 rrrrr001101rrrrr gr [reg2] gr [reg2] ? gr [reg1] subr reg1, reg2 rrrrr001100rrrrr gr [reg2] gr [reg1] ? gr [reg2] mulh reg1, reg2 rrrrr000111rrrrr gr [reg2] gr [reg2] note gr [reg1] note (signed multiplication) mulh imm5, reg2 rrrrr010111iiiii gr [reg2] gr [reg2] note sign-extend (imm5) (signed multiplication) mulhi imm16, reg1, reg2 rrrrr110111rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] note imm16 (signed multiplication) divh reg1, reg2 rrrrr000010rrrrr gr [reg2] gr [reg2] gr [reg1] note (signed division) cmp reg1, reg2 rrrrr001111rrrrr result gr [reg2] ? gr [reg1] cmp imm5, reg2 rrrrr010011iiiii result gr [reg2] ? sign-extend (imm5) arithmetic operation setf cccc, reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr [reg2] 00000001h else gr [reg2] 00000000h satadd reg1, reg2 rrrrr000110rrrrr gr [reg2] saturated (gr [reg2] + gr [reg1]) satadd imm5, reg2 rrrrr010001iiiii gr [reg2] saturated (gr [reg2] + sign- extend (imm5)) satsub reg1, reg2 rrrrr000101rrrrr gr [reg2] saturated (gr [reg2] ? gr [reg1]) satsubi imm16, reg1, reg2 rrrrr110011rrrrr iiiiiiiiiiiiiiii gr [reg2] saturated (gr [reg1] ? sign- extend (imm16)) saturated operation satsubr reg1, reg2 rrrrr000100rrrrr gr [reg2] saturated (gr [reg1] ? gr [reg2]) tst reg1, reg2 rrrrr001011rrrrr result gr [reg2] and gr [reg1] 0 or reg1, reg2 rrrrr001000rrrrr gr [reg2] gr [reg2] or gr [reg1] 0 ori imm16, reg1, reg2 rrrrr110100rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] or zero-extend (imm16) 0 and reg1, reg2 rrrrr001010rrrrr gr [reg2] gr [reg2] and gr [reg1] 0 logic operation andi imm16, reg1, reg2 rrrrr110110rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] and zero-extend (imm16) 0 0 note only the lower halfword data is valid.
appendix c list of instruction sets user?s manual u12768ej4v1ud 478 instruction set list (3/4) flag instruction group mnemonic operand opcode operation cy ov s z sa t xor reg1, reg2 rrrrr001001rrrrr gr [reg2] gr [reg2] xor gr [reg1] 0 xori imm16, reg1, reg2 rrrrr110101rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] xor zero-extend (imm16) 0 not reg1, reg2 rrrrr000001rrrrr gr [reg2] not (gr [reg1]) 0 shl reg1, reg2 rrrrr111111rrrrr 0000000011000000 gr [reg2] gr [reg2] logically shift left by gr [reg1] 0 shl imm5, reg2 rrrrr010110iiiii gr [reg2] gr [reg2] logically shift left by zero-extend (imm5) 0 shr reg1, reg2 rrrrr111111rrrrr 0000000010000000 gr [reg2] gr [reg2] logically shift right by gr [reg1] 0 shr imm5, reg2 rrrrr010100iiiii gr [reg2] gr [reg2] logically shift right by zero-extend (imm5) 0 sar reg1, reg2 rrrrr111111rrrrr 0000000010100000 gr [reg2] gr [reg2] arithmetically shift right by gr [reg1] 0 logic operation sar imm5, reg2 rrrrr010101iiiii gr [reg2] gr [reg2] arithmetically shift right by zero-extend (imm5) 0 jmp [reg1] 00000000011rrrr r pc gr [reg1] jr disp22 0000011110dddddd ddddddddddddddd0 note 1 pc pc + sign-extend (disp22) jarl disp22, reg2 rrrrr11110dddddd ddddddddddddddd0 note 1 gr [reg2] pc + 4 pc pc + sign-extend (disp22) jump bcond disp9 ddddd1011dddcccc note 2 if conditions are satisfied then pc pc + sign-extend (disp9) set1 bit#3, disp16 [reg1] 00bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 1) clr1 bit#3, disp16 [reg1] 10bbb111110rrrr r dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 0) not1 bit#3, disp16 [reg1] 01bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) bit manipulate tst1 bit#3, disp16 [reg1] 11bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) notes 1. ddddddddddddddddddddd is the higher 21 bits of dip22. 2. dddddddd is the higher 8 bits of disp9.
appendix c list of instruction sets user?s manual u12768ej4v1ud 479 instruction set list (4/4) flag instruction group mnemonic operand opcode operation cy ov s z sa t regid = eipc, fepc regid = eipsw, fepsw ldsr reg2, regid rrrrr111111rrrrr 0000000000100000 note sr [regid] gr [reg2] regid = psw stsr regid, reg2 rrrrr111111rrrrr 0000000001000000 gr [reg2] sr [regid] trap vector 00000111111iiiii 0000000100000000 eipc pc + 4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (vector = 00h to 0fh) 00000050h (vector = 10h to 1fh) reti 0000011111100000 0000000101000000 if psw.ep = 1 then pc eipc psw eipsw else if psw.np = 1 then pc fepc psw fepsw else pc eipc psw eipsw r r r r r halt 0000011111100000 0000000100100000 stops di 0000011111100000 0000000101100000 psw.id 1 (maskable interrupt disabled) ei 1000011111100000 0000000101100000 psw.id 0 (maskable interrupt enabled) special nop 0000000000000000 uses 1 clock cycle without doing anything note the opcode of this instruction uses the field of reg1 even though the source register is shown as reg2 in the above table. therefore, t he meaning of the register specification for mnemonic description and opcode is different from that of the other instructions. rrrrr = regid specification rrrrr = reg2 specification
user?s manual u12768ej4v1ud 480 appendix d index [number] 16-bit compare r egister 23 ------------------------------- 205 16-bit compare r egister 45 ------------------------------- 205 16-bit count er 23 ------------------------------------------- 205 16-bit count er 45 ------------------------------------------- 205 16-bit timers ------------------------------------------------- 153 16-bit timer mode control register n ------------------- 158 16-bit timer operatio n -------------------------------------- 166 16-bit timer output control registers 0, 1 -------------- 161 16-bit timer registers 0, 1 --------------------------------- 155 3-wire serial i/o --------------------------------------------- 221 3-wire serial i/o mode ------------------------------------ 221 8-bit compare regi sters 2 to 5---------------------------- 191 8-bit counters 2 to 5 ---------------------------------------- 191 8-bit pwm output ------------------------------------------- 202 8-bit timers---------------------------------------------------- 189 8-bit timer mode control registers 2 to 5 -------------- 195 8-bit timer operation ---------------------------------------- 197 [a] a/d conversion resu lt register -------------------------- 310 a/d conversion result register h ----------------------- 310 a/d converter ----------------------------------------------- 308 a/d converter m ode regist er ---------------------------- 312 a/d converter oper ation m ode--------------------------- 319 a1 to a4 --------------------------------------------------------52 a13 to a15 -----------------------------------------------------47 a16 to a21 -----------------------------------------------------49 a5 to a12 -------------------------------------------------------52 access clock ---------------------------------------------------90 ack detector------------------------------------------------- 232 ack output ci rcuit------------------------------------------- 232 ack si gnal---------------------------------------------------- 247 ad0 to ad7 ----------------------------------------------------48 ad8 to ad15 --------------------------------------------------48 adcr --------------------------------------------------------- 310 adcrh ------------------------------------------------------- 310 address (i 2 c bus) ------------------------------------------- 245 address match det ection me thod ---------------------- 270 address s pace ------------------------------------------------66 adic ----------------------------------------------------------- 124 adm ----------------------------------------------------------- 312 ads ------------------------------------------------------------ 315 adtrg ---------------------------------------------------------44 analog input channel specif ication register ---------- 315 ani0 to ani11 ------------------------------------------ 49, 311 applicat ions ---------------------------------------------------- 30 arbitrat ion ---------------------------------------------------- 271 area -------------------------------------------------------------- 70 area num ber ------------------------------------------------- 422 asck0 ---------------------------------------------------------- 45 asck1 ---------------------------------------------------------- 46 asim0, asim1 ---------------------------------------------- 288 asis0, asis1 ----------------------------------------------- 290 astb ----------------------------------------------------------- 51 asynchronous serial interface --------------------------- 286 asynchronous serial interface mode ------------------ 295 asynchronous serial interface mode registers 0, 1 ------------------------------------------------ 288 asynchronous serial interface status registers 0, 1 ------------------------------------------------ 290 av dd ----------------------------------------------------- 53, 311 av ref ---------------------------------------------------- 53, 311 av ss ------------------------------------------------------ 53, 311 [b] baud rate generator control registers 0, 1 ----------- 291 baud rate generator mode cont rol registers 0, 01 - 292 baud rate generator mode control register 1 ------- 293 bcc ------------------------------------------------------------- 95 bcu ------------------------------------------------------------- 35 brgc0, brgc1 ------------------------------------------- 291 brgmc0, brgmc01 ------------------------------------ 292 brgmc1 ----------------------------------------------------- 293 bus access ----------------------------------------------------- 90 bus control function ----------------------------------------- 89 bus control pins ---------------------------------------------- 89 bus contro l unit ----------------------------------------------- 35 bus cycle control register ---------------------------------- 95 bus hold f unction -------------------------------------------- 96 bus hold pr ocedure ------------------------------------------ 97 bus priority -------------------------------------------------- 105 bus timi ng ----------------------------------------------------- 98 bus width ------------------------------------------------------ 91 bv dd ------------------------------------------------------------ 53 bv ss ------------------------------------------------------------- 53 byte access --------------------------------------------------- 91 [c] calling device inter nal processing---------------------- 425 calling param eter------------------------------------------- 419 capture/compare contro l registers 0, 1 -------------- 156
appendix d index user?s manual u12768ej4v1ud 481 capture/compare register n0 --------------------------- 156 capture/compare register n1 --------------------------- 157 cascade connection (16-bit timer) mode ------------ 205 cautions on power save function----------------------- 151 cg --------------------------------------------------------------- 36 channel contro l block ------------------------------------- 331 clkout ------------------------------------------------------- 53 clock generation function -------------------------------- 138 clock generator (cg) --------------------------------------- 36 clock output f unction ------------------------------------- 139 clock sele ctor ----------------------------------------------- 231 command regi ster ------------------------------------------- 88 communication command ------------------------------- 411 communication operation -------------------------------- 277 communication re servati on ----------------------------- 273 communication system ---------------------------------- 404 conversion time--------------------------------------------- 329 cpu ------------------------------------------------------------- 35 cpu address space ----------------------------------------- 66 cpu register set --------------------------------------------- 60 cr00, cr 10 ------------------------------------------------ 156 cr01, cr 11 ------------------------------------------------ 156 cr20 to cr50 ---------------------------------------------- 191 cr23 ---------------------------------------------------------- 205 cr45 ---------------------------------------------------------- 205 crc0, crc1 ----------------------------------------------- 160 csi0 to csi2 ------------------------------------------------ 223 csic0 to csic2 ------------------------------------------- 124 csim0 to csim2 ------------------------------------------- 223 csis0 to csis2 -------------------------------------------- 223 [d] data communica tion timi ng ------------------------------ 279 data hold time corre ction circuit ------------------------ 232 data space ----------------------------------------- 68, 79, 105 data wait contro l register ---------------------------------- 93 dbc0 to dbc2 --------------------------------------------- 335 dchc0 to dchc2 ----------------------------------------- 336 dioa0 to dioa2 ------------------------------------------- 332 differential linear ity error---------------------------------- 328 dma functions ---------------------------------------------- 330 dma byte count registers 0 to 2 ----------------------- 335 dma channel control registers 0 to 2 ----------------- 336 dma internal ram address registers 0 to 2 -------- 332 dma peripheral i/o address registers 0 to 2 -------- 332 dma transfer request control block -------------------- 331 dmaic0 to dmaic2 -------------------------------------- 124 dra0 to dra2 --------------------------------------------- 332 dstb ----------------------------------------------------------- 50 dwc ------------------------------------------------------------ 93 [e] ecr ------------------------------------------------------------- 62 edge detection function of ex ternal interrupt request input pi n ----------------------------------------------------114 egn0 --------------------------------------------------- 114, 351 egp0 --------------------------------------------------- 114, 351 eipc ------------------------------------------------------------ 62 eipsw --------------------------------------------------------- 62 electrical spec ificati ons------------------------------------434 ep flag ---------------------------------------------------------129 erase uni t -----------------------------------------------------398 error detec tion ----------------------------------------------270 exception trap -----------------------------------------------129 extension code ---------------------------------------------270 external event counter ----------------------------- 176, 200 external expans ion m ode --------------------------------- 77 external memo ry area ------------------------------------- 75 external wait function -------------------------------------- 94 [f] falling edge specification register 0------------- 114, 351 fepc ----------------------------------------------------------- 62 fepsw -------------------------------------------------------- 62 flash info rmation--------------------------------------------421 flash memory -----------------------------------------------398 flash memory control -------------------------------------410 flash memory programming by self-programming -413 flash memory programming mode ---------------65, 410 flash programming mode control register ------------423 flow of acquiring fl ash information ---------------------431 flow of erasing flash memory----------------------------428 flpmc---------------------------------------------------------423 full-scale error-----------------------------------------------328 function block c onfiguration ------------------------------ 34 [g] general-purpose register ---------------------------------- 61 [h] halfword access --------------------------------------------- 91 halt mode --------------------------------------------------144 hardware environment hardware start --------------------------------------- 308, 320 hldak --------------------------------------------------------- 51 hldrq -------------------------------------------------------- 51 how to read a/d converter characteristic table------326
appendix d index user?s manual u12768ej4v1ud 482 [i] i 2 c bus -------------------------------------------------------- 228 i 2 c bus definitions and control methods --------------- 244 i 2 c bus m ode ------------------------------------------------ 228 i 2 c bus mode f unction ------------------------------------- 243 i 2 c interrupt request --------------------------------------- 251 ic -----------------------------------------------------------------54 id flag --------------------------------------------------------- 126 idle m ode --------------------------------------------------- 147 idle state insert ion func tion --------------------------------95 iic clock select register 0 -------------------------------- 241 iic control register 0 --------------------------------------- 234 iic function expansi on register 0 ----------------------- 241 iic shift register 0 ----------------------------------- 231, 242 iic status register 0 ---------------------------------------- 238 iic0 ------------------------------------------------------------ 242 iicc0 ---------------------------------------------------------- 234 iiccl0 -------------------------------------------------------- 241 iics0 ---------------------------------------------------------- 238 iicx0 ---------------------------------------------------------- 241 illegal opcode ----------------------------------------------- 129 image -----------------------------------------------------------67 input voltage and conv ersion result -------------------- 318 in-service priority register -------------------------------- 125 intc -------------------------------------------------------------35 integral linear ity error -------------------------------------- 329 internal blo ck diagram ---------------------------------------34 internal flash memory area ---------------------------------70 internal ra m area -------------------------------------------73 internal ro m area -------------------------------------------70 internal unit -----------------------------------------------------35 internal veri fy flow ------------------------------------------ 430 interrupt contro l regist er ---------------------------------- 122 interrupt control register bi t manipulation instructions during dma tr ansfer ------------------------------------- 137 interrupt controller -------------------------------------------35 interrupt latency time -------------------------------------- 135 interrupt request (intiic0) generation timing and wait control------------------------------------------------------- 269 interrupt request signal generator ---------------------- 232 interrupt request valid timing after ei instruction ---- 136 interrupt signal generator --------------------------------- 232 interrupt sour ce list ----------------------------------------- 107 interrupt source register ------------------------------------62 interrupt status saving registers --------------------------62 interrupt/exception processing function --------------- 106 interrupt/except ion tabl e ------------------------------------72 interval timer ---------------------------- 166, 197, 205, 211 interval timer mode ---------------------------------------- 214 intp0 to intp6 ---------------------------------------------- 44 introducti on----------------------------------------------------- 27 ispr ---------------------------------------------------------- 125 [l] lben ------------------------------------------------------------ 50 [m] main clock o scillator --------------------------------------- 138 mam ------------------------------------------------------------ 78 maskable inte rrupts --------------------------------------- 115 master oper ation-------------------------------------------- 277 memory address output mode register ----------------- 78 memory block function ------------------------------------- 92 memory boundary operat ion condition --------------- 105 memory expansion m ode register ----------------------- 77 memory map -------------------------------------------------- 69 mm -------------------------------------------------------------- 77 multiple in terrupt ------------------------------------------- 132 [n] nmi -------------------------------------------------------------- 44 nmi status saving registers ------------------------------- 62 noise elimination of external interrupt request input pin113 non-maskable in terrupt ---------------------------------- 109 non-port pins -------------------------------------------------- 41 np flag -------------------------------------------------------- 113 [o] off-board progr amming ---------------------------------- 399 on-board progr amming ---------------------------------- 399 on-chip peripher al i/o area ------------------------------- 74 one-shot pulse output ------------------------------------ 179 operation in power save mode --------------------------- 97 operation mode ---------------------------------------------- 65 operation mode regi sters 0 to 2 ----------------------- 223 operation stop mode ----------- 221, 225, 228, 286, 294 ordering info rmation ----------------------------------------- 30 oscillation stabiliz ation ti me ----------------------------- 150 oscillation stabilization time select register ---143, 215 osts -------------------------------------------- 143, 215, 220 outline of self -progra mming ----------------------------- 413 outline of self-programming interface ----------------- 415 output latch -------------------------------------------------- 342 overall error-------------------------------------------------- 326 [p] p0 -------------------------------------------------------------- 348 p00 to p07 ----------------------------------------------------- 44
appendix d index user?s manual u12768ej4v1ud 483 p1 -------------------------------------------------------------- 353 p10 ------------------------------------------------------------ 383 p10 to p15 ---------------------------------------------------- 45 p100 to p107 ------------------------------------------------- 52 p11 ------------------------------------------------------------ 387 p110 to p114 ------------------------------------------------- 52 p12 ------------------------------------------------------------ 390 p120 ------------------------------------------------------------ 53 p2 -------------------------------------------------------------- 359 p20 to p27 ---------------------------------------------------- 46 p3 -------------------------------------------------------------- 367 p30 to p37 ---------------------------------------------------- 47 p4 -------------------------------------------------------------- 372 p40 to p47 ---------------------------------------------------- 48 p5 -------------------------------------------------------------- 372 p50 to p57 ---------------------------------------------------- 47 p6 -------------------------------------------------------------- 375 p60 to p65 ---------------------------------------------------- 49 p7 -------------------------------------------------------------- 377 p70 to p77 ---------------------------------------------------- 49 p8 -------------------------------------------------------------- 377 p80 to p83 ---------------------------------------------------- 49 p9 -------------------------------------------------------------- 379 p90 to p96 ---------------------------------------------------- 50 package dra wing ------------------------------------------- 460 pc ---------------------------------------------------------------- 61 pcc ----------------------------------------------------------- 140 periods when interrupt is not acknowledged -------- 135 peripheral i/o registers ------------------------------------- 81 pf1 ------------------------------------------------------------ 355 pf10 ---------------------------------------------------------- 385 pf2 ------------------------------------------------------------ 361 pic0 to pic6 ------------------------------------------------ 124 pin configur ation ---------------------------------------------- 31 pin connec tion ---------------------------------------------- 407 pin functions -------------------------------------------------- 38 pin function de scription ------------------------------------- 44 pin functi on list ------------------------------------------------ 38 pin i/o circuits ------------------------------------------------ 57 pin stat us ------------------------------------------------------- 43 pm0 ----------------------------------------------------------- 350 pm1 ----------------------------------------------------------- 354 pm10 --------------------------------------------------------- 384 pm11 --------------------------------------------------------- 388 pm12 --------------------------------------------------------- 391 pm2 ----------------------------------------------------------- 360 pm3 ----------------------------------------------------------- 368 pm4 ----------------------------------------------------------- 373 pm5 ----------------------------------------------------------- 373 pm6 ------------------------------------------------------------376 pm9 ------------------------------------------------------------380 pmc12 --------------------------------------------------------391 port 0 ----------------------------------------------------------348 port 0 mode r egister ---------------------------------------350 port 1 ----------------------------------------------------------353 port 1 function register ------------------------------------355 port 1 mode r egister ---------------------------------------354 port 10 --------------------------------------------------------383 port 10 function register ----------------------------------385 port 10 mode r egister -------------------------------------384 port 11 --------------------------------------------------------387 port 11 mode r egister -------------------------------------388 port 12 --------------------------------------------------------390 port 12 mode contro l register ---------------------------391 port 12 mode r egister -------------------------------------391 port 2 ----------------------------------------------------------359 port 2 function register ------------------------------------361 port 2 mode r egister ---------------------------------------360 port 3 ----------------------------------------------------------367 port 3 mode r egister ---------------------------------------368 port 4 ----------------------------------------------------------372 port 4 mode r egister ---------------------------------------373 port 5 ----------------------------------------------------------372 port 5 mode r egister ---------------------------------------373 port 6 ----------------------------------------------------------375 port 6 mode r egister ---------------------------------------376 port 7 ----------------------------------------------------------377 port 8 ----------------------------------------------------------377 port 9 ----------------------------------------------------------379 port 9 mode r egister ---------------------------------------380 port function --------------------------------------------------348 port function operatio n-------------------------------------396 port pins -------------------------------------------------------- 38 power save contro l register ------------------------------142 power save f unctions -------------------------------------143 power s upply-------------------------------------------------409 ppg output --------------------------------------------------168 prcmd -------------------------------------------------------- 88 prescaler mode regi sters 0 and 1-----------------------162 prescaler mode regi sters 1 and 11 ---------------------164 priority control -----------------------------------------------132 priorities of interrupts and exceptions -----------------132 priorities of maskable interrupts-------------------------118 prm0, prm01 ----------------------------------------------162 prm1, prm11 ----------------------------------------------164 processor clock cont rol register ------------------------140 program counter --------------------------------------------- 61 program register set ---------------------------------------- 61
appendix d index user?s manual u12768ej4v1ud 484 program space ------------------------------------ 68, 79, 105 program status word ----------------------------------------63 programmable wait function -------------------------------93 programming env ironment ------------------------------- 404 programming method ------------------------------------- 410 psc ------------------------------------------------------------ 142 psw -------------------------------------------------------------63 pu0 ------------------------------------------------------------ 350 pu1 ------------------------------------------------------------ 355 pu10 ---------------------------------------------------------- 385 pu11 ---------------------------------------------------------- 388 pu2 ------------------------------------------------------------ 361 pu3 ------------------------------------------------------------ 368 pull-up resistor opti on register 0 ------------------------ 350 pull-up resistor opti on register 1 ------------------------ 355 pull-up resistor opti on register 10 ---------------------- 385 pull-up resistor opti on register 11 ---------------------- 388 pull-up resistor opti on register 2 ------------------------ 361 pull-up resistor opti on register 3 ------------------------ 368 pulse width meas urement ------------------------------- 169 [q] quantization error------------------------------------------- 327 [r] r/w --------------------------------------------------------------50 ram -------------------------------------------------------------35 ram parameter contents --------------------------------- 420 rd ---------------------------------------------------------------51 reading from i/o port-------------------------------------- 396 real-time output buffer register h --------------------- 342 real-time output buffer register l ---------------------- 342 real-time output function -------------------------------- 340 real-time output port control register ----------------- 344 real-time output port mode register ------------------- 343 receive buffer regi sters 0, 1 ---------------------------- 287 receive shift regi sters 0, 1 ------------------------------ 287 reception c ontroller ---------------------------------------- 288 recommended connection of unused pins ------------55 recommended solderi ng conditi ons ------------------- 462 recommended use of address space ------------------79 relationship between programmable wait and external wait ------------------------------------------------------------94 reset ----------------------------------------------------------53 reset func tion ----------------------------------------------- 397 resoluti on ---------------------------------------------------- 326 resources used -------------------------------------------- 412 rising edge specification register 0 ------------ 114, 351 rom -------------------------------------------------------------35 rtbh --------------------------------------------------------- 342 rtbl ---------------------------------------------------------- 342 rto ----------------------------------------------------------- 340 rtp ------------------------------------------------------------- 36 rtp0 to rtp7 ------------------------------------------------ 52 rtpc --------------------------------------------------------- 344 rtpm --------------------------------------------------------- 343 rtptrg ------------------------------------------------------- 44 rx0, rx 1 ---------------------------------------------------- 287 rxb0, rxb1 ------------------------------------------------ 287 rxd0 ----------------------------------------------------------- 45 rxd1 ----------------------------------------------------------- 46 [s] sample & hold circuit -------------------------------------- 310 sampling time ----------------------------------------------- 329 sar ----------------------------------------------------------- 310 sck0, sck1 -------------------------------------------------- 45 sck2 ------------------------------------------------------------ 46 scl -------------------------------------------------------------- 45 sda -------------------------------------------------------------- 45 self-programmi ng erro r ----------------------------------- 421 self-programmi ng functi on ------------------------------- 414 self-programming function number -------------------- 418 self-programmi ng libra ry --------------------------------- 432 serial clock controller-------------------------------------- 232 serial clock counter --------------------------------------- 232 serial clock select registers 0 to 2 --------------------- 223 serial clock wait controller-------------------------------- 232 serial i/o shift registers 0 to 2 -------------------------- 222 serial interfac e functi on ---------------------------------- 221 serial interf ace pi n ----------------------------------------- 407 serial operation mode registers 0 to 2 --------------- 223 seric0, seric1 ------------------------------------------ 124 series resistor string --------------------------------------- 310 setting when port pin is used as alternate function 393 si0, si1 --------------------------------------------------------- 45 si2---------------------------------------------------------------- 46 single-chip mode -------------------------------------------- 65 sio -------------------------------------------------------------- 36 sio0 to sio2 ----------------------------------------------- 222 slave address regi ster 0 ---------------------------231, 242 slave operat ion --------------------------------------------- 278 so latch ------------------------------------------------------ 231 so0, so1 ------------------------------------------------------ 45 so2 ------------------------------------------------------------- 46 software env ironment ------------------------------------- 417 software exc eption ---------------------------------------- 127 software start -----------------------------------------308, 321
appendix d index user?s manual u12768ej4v1ud 485 software stop mode ------------------------------------ 148 specific register ---------------------------------------------- 86 square wave out put ---------------------------------178, 201 sric1 -------------------------------------------------------- 124 standby func tion ------------------------------------------- 307 start condi tion ---------------------------------------------- 244 start condition detector ----------------------------------- 232 stic0, stic1 ----------------------------------------------- 124 stop condi tion ---------------------------------------------- 248 stop condition detector------------------------------------ 232 subclock osc illator ----------------------------------------- 138 successive approximat ion register -------------------- 310 successive writ ing fl ow ----------------------------------- 429 sva0 ----------------------------------------------------231, 242 syc ------------------------------------------------------------- 90 sys ------------------------------------------------------------- 88 system control register ------------------------------------- 90 system register set ------------------------------------------ 62 system status register -------------------------------------- 88 [t] tcl2 to tcl5, tcl21 to tcl51------------------------ 193 ti00, ti01, ti10, ti11, ti4, ti5 -------------------------- 47 ti2, ti3 --------------------------------------------------------- 46 timer clock select registers 2 to 5, 21 to 51 --------- 193 timer/counter function ------------------------------------ 153 tm0, tm1 ---------------------------------------------------- 153 tm23 ---------------------------------------------------------- 205 tm2 to tm5 ------------------------------------------------- 191 tm45 ---------------------------------------------------------- 205 tmc0, tmc1 ----------------------------------------------- 158 tmc2 to tmc5 --------------------------------------------- 195 tmic00 ------------------------------------------------------- 124 tmic01 ------------------------------------------------------- 124 tmic10 ------------------------------------------------------- 124 tmic11 ------------------------------------------------------- 124 tmic2 to tmic5 ------------------------------------------- 124 to0, to1, to4, to5 --------------------------------------- 47 to2, to3 ------------------------------------------------------ 46 toc0, toc1 ------------------------------------------------ 161 transfer direction specification ------------------------- 246 transmit shift registers 0, 1 ----------------------------- 287 transmission c ontrolle r ----------------------------------- 288 txd0 ------------------------------------------------------------ 45 txd1 ------------------------------------------------------------ 46 txs0, txs1 ------------------------------------------------- 287 [u] uart0, uart1 ---------------------------------------------286 uben ----------------------------------------------------------- 50 [v] v dd -------------------------------------------------------------- 54 voltage com parator -----------------------------------------310 v pp -------------------------------------------------------------- 54 v ss -------------------------------------------------------------- 54 [w] wait ----------------------------------------------------------- 53 wait function -------------------------------------------------- 93 wait signal (i 2 c bus)----------------------------------------249 wakeup cont roller-------------------------------------------231 wakeup func tion --------------------------------------------272 watch timer function ---------------------------------------208 watch timer mode control register -------------- 126, 210 watchdog ti mer ---------------------------------------------213 watchdog timer clock select register ------------------216 watchdog time r mode -------------------------------------214 watchdog timer mode register ------------------- 126, 217 wdcs ---------------------------------------------------------216 wdtic --------------------------------------------------------124 wdtm -------------------------------------------------- 126, 217 word access -------------------------------------------------- 91 wraparound of cpu addr ess space -------------------- 68 wrh ------------------------------------------------------------ 51 writing by flas h programmer ----------------------------399 writing to i/o port -------------------------------------------396 wrl ------------------------------------------------------------ 51 wtic ----------------------------------------------------------124 wtiic ---------------------------------------------------------124 wtm -----------------------------------------------------------210 [x] x1 --------------------------------------------------------------- 53 x2 --------------------------------------------------------------- 53 xt1 ------------------------------------------------------------- 52 xt2 ------------------------------------------------------------- 53 [z] zero-scale error ---------------------------------------------327
user?s manual u12768ej4v1ud 486 appendix e revision history the following table shows the revision history up to this editi on. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/7) edition major revision from pr evious edition applied to: deletion of pd703015, 703015y, 70f3017, and 70f3017y addition of pd703014a, 703014ay, 703015a, 703015ay, 703017a, 703017ay, 70f3017a, and 70f3017ay throughout 1.2 features deletion and addition of products, m odification of minimum instruction execution time 1.4 ordering information deletion and addition of products 1.5 pin configuration deletion and addition of products 1.6.1 internal block diagram deletion and addition of products 1.6.2 internal units (3) rom , (4) ram , (10) serial interface (sio) deletion and addition of products introduction 2.1 (2) non-port pins deletion and addition of products in note 2.3 (2) (b) (iv) sda , (v) scl deletion and addition of products, (23) v pp , (24) ic deletion and addition of products 2.4 pin i/o circuits and recommended connection of unused pins deletion of items av dd and av ss pins, modification of recommended connection method of av ref pin chapter 2 pin functions 3.1 features modification of minimum instruction execution time 3.2 cpu register set modification of use of r2 3.2.1 (1) general registers modification of use and operati on of r2 and addition of note 2 3.3 (2) flash memory programming mode deletion and addition of products figure 3-9 memory map correction 3.4.5 (1) internal rom/internal flash memory area addition table 3-3 interrupt/exception table deletion and addition of products in note 3.4.5 (2) internal ram area addition figure 3-16 external memory area (when expanded to 64 kb, 256 kb, or 1 mb) modification figure 3-17 external memory area (when expanded to 4 mb) modification figure 3-18 memory expansion mode register (mm) addition of caution 3.4.6 (2) memory address output mode register (mam) addition of description figure 3-20 application example of wrap-around modification 3.4.8 peripheral i/o registers addition of prm01, prm11, tcl21, tcl31, tcl41, tcl51, brgmc01, iicx0, and note chapter 3 cpu functions 3rd edition table 5-1 interrupt source list deletion and addition of products in note 2 chapter 5 interrupt/exce ption processing function
appendix e revision history user?s manual u12768ej4v1ud 487 (2/7) edition major revision from pr evious edition applied to: 6.1 (1) main system clock oscillator modification of maximum operating frequency and addition of caution 2 figure 6-2 processor clock control register (pcc) modification of bit 7, addition of bit 5 (mfrc) and caution 3 6.3.1 (1) (a) example of main clock operation sub clock operation setup , (b) example of sub clock operation main clock operation setup addition 6.4.1 (3) software stop mode deletion of part of description table 6-1 operating statuses in halt mode correction of items uart0 and uart1, deletion and addition of products in note table 6-2 operating statuses in idle mode correction of items uart0 and uart1, deletion and addition of products in note 6.4.4 (1) settings and operating states deletion of part of description table 6-3 operating statuses in software stop mode correction of items uart0 and uart1, deletion and addition of products in note 6.4.4 (2) cancellation of software stop mode deletion of part of description chapter 6 clock generation function figure 7-1 block diagram of tm0 and tm1 modification table 7-1 configuration of timers 0 and 1 addition of prescaler mode registers 01, 11 (prm01, prm11) table 7-4 valid edge of tin0 pin and capture trigger of crn1 addition 7.1.4 timer 0, 1 control registers addition of prescaler mode register n1 (prmn1) figure 7-3 capture/compare control registers 0, 1 (crc0, crc1) addition of caution 4 figure 7-4 16-bit timer output control registers 0, 1 (toc0, toc1) correction of note and addition of caution 4 7.1.4 (4) prescaler mode registers 0, 01 (prm0, prm01) addition of prm01 register figure 7-5 prescaler mode register 0 (prm0) addition of note 2 figure 7-6 prescaler mode register 01 (prm01) addition 7.1.4 (5) prescaler mode registers 1, 11 (prm1, prm11) addition of prm11 register figure 7-7 prescaler mode register 1 (prm1) addition of note 2 figure 7-8 prescaler mode register 11 (prm11) addition figure 7-10 configuration of interval timer correction 7.2.3 (1) pulse width measurement with fr ee running counter and one capture register addition of prm01 and prm11 registers figure 7-14 configuration for pulse widt h measurement with free running counter addition of prm01 and prm11 registers in note 7.2.3 (2) measurement of two pulse widths with free running counter addition of prm01 and prm11 registers 7.2.3 (3) pulse width measurement with free running counter and two capture registers addition of prm01 and prm11 registers 7.2.3 (4) pulse width measurement by restarting addition of prm01 and prm11 registers 3rd edition 7.2.4 operation as external event counter addition of prm01 and prm11 registers chapter 7 timer/counte r function
appendix e revision history user?s manual u12768ej4v1ud 488 (3/7) edition major revision from pr evious edition applied to: figure 7-24 configuration of external event counter addition of prm01 and prm11 registers in note figure 7-28 control register settings for one-shot pulse output with software trigger addition of caution 7.2.7 (2) setting 16-bit capture/compare register , (7) <2> , (8) conflicting operations , (9) timer operation , (10) capture operation , (11) compare operation , (12) edge detection addition 7.3.1 functions addition of caution figure 7-36 block diagram of tm2 to tm5 correction table 7-5 configuration of timers 2 to 5 addition of timer clo ck select register n1 (tcln1) 7.3.2 (1) 8-bit counters 2 to 5 (tm2 to tm5) addition of description 7.3.2 (2) 8-bit compare registers 2 to 5 (cr20 to cr50) addition of description 7.3.3 timer n control register addition of tcln1 register 7.3.3 (1) timer clock select registers 2, 21, 3, 31, 4, 41, 5, 51 (tcl2 to tcl5 and tcl21 to tcl51) addition of tcln1 register figure 7-37 tm2, tm3 timer clock select registers 2, 21, 3, 31 (tcl2, tcl21, tcl3, and tcl31) addition of tcln1 register figure 7-38 tm4, tm5 timer clock select registers 4, 41, 5, 51 (tcl4, tcl41, tcl5, and tcl51) addition of tcln1 register figure 7-39 8-bit timer mode control registers 2 to 5 (tmc2 to tmc5) addition of note figure 7-42 timing of square wave output operation addition 7.4.5 (1) cascade connection (16-bit timer) mode addition of description chapter 7 timer/counter function 8.4.3 cautions addition chapter 8 watch timer figure 9-1 block diagram of watchdog timer correction table 9-1 runaway detection time of watchdog timer addition of runaway detection time when f xx = 10 mhz, f xx = 2 mhz table 9-2 interval time of interval timer addition of interval time when f xx = 10 mhz, f xx = 2 mhz figure 9-2 oscillation stabilization time select register (osts) addition of oscillation stabilization time when f xx = 10 mhz, f xx = 2 mhz figure 9-3 watchdog timer clock select register (wdcs) addition of overflow time of watchdog timer/interval timer when f xx = 10 mhz, f xx = 2 mhz figure 9-4 watchdog timer mode register (wdtm) correction of caution 9.4.1 operating as watchdog timer deletion of part of description and correction of caution 1 table 9-4 runaway detection time of watchdog timer addition of runaway detection time when f xx = 10 mhz, f xx = 2 mhz 9.4.2 operating as interval timer deletion of part of description and correction of caution 1 3rd edition table 9-5 interval time of interval timer addition of interval time when f xx = 10 mhz, f xx = 2 mhz chapter 9 watchdog timer
appendix e revision history user?s manual u12768ej4v1ud 489 (4/7) edition major revision from pr evious edition applied to: figure 9-5 oscillation stabilization time select register (osts) addition of oscillation stabilization time when f xx = 10 mhz, f xx = 2 mhz chapter 9 watchdog timer 10.1 overview deletion and addition of products in note figure 10-2 serial operation mode registers 0 to 2 (csim0 to csim2) addition of notes figure 10-5 settings of csimn (3-wire serial i/o mode) addition of note 10.3 i 2 c bus ( pd703014ay, 703015ay, 703017ay, 70f3017ay) deletion and addition of products figure 10-7 block diagram of i 2 c correction table 10-2 configuration of i 2 c addition of iic function expansion register 0 (iicx0) 10.3.2 i 2 c control registers addition of iic function expansion register 0 (iicx0) figure 10-9 iic control register 0 (iicc0) (3/4) addition of condition of stt = 0 and deletion of note figure 10-9 iic control register 0 (iicc0) (4/4) addition of description and deletion of note 2 figure 10-10 iic status register 0 (iics0) (2/3) addition of note 10.3.2 (3) iic clock select register 0 (iiccl0) addition of remark figure 10-11 iic clock select register 0 (iiccl0) addition of operation description of bit 3 (smc) and bit 2 (dfc) 10.3.2 (4) iic function expansion register 0 (iicx0) addition table 10-3 settings of transfer clock addition of iic communication frequency when f xx = 20 mhz 10.3.4 (4) acknowledge signal (ack) addition of description 10.3.5 i 2 c interrupt request (intiic0) addition of description 10.3.6 (4) wait cancellation method addition of cancellation method table 10-7 wait periods modification of wait period when smc, cl1, cl0 = 010 and 110 figure 10-27 master operation flow chart correction table 10-8 configuration of uartn addition of baud rate generator mode control register 01 (brgmc01) 10.4.2 uartn control registers addition of brgmc01 register 10.4.2 (4) baud rate generator mode control registers 0, 01 (brgmc0, brgmc01) addition of brgmc01 register figure 10-35 baud rate generator mode control registers 0, 01 (brgmc0, brgmc01) addition of brgmc01 register 10.4.4 (1) register settings addition of brgmc01 register 10.4.4 (2) generation of baud rate transmit/receive clock using main clock correction table 10-9 relationship between main clock and baud rate correction chapter 10 serial interface function figure 11-2 a/d converter mode register (adm) correction of conversion time chapter 11 a/d converter 3rd edition figure 12-2 dma internal ram address registers 0 to 2 (dra0 to dra2) addition of caution chapter 12 dma functions
appendix e revision history user?s manual u12768ej4v1ud 490 (5/7) edition major revision from pr evious edition applied to: figure 12-3 correspondence between dran setup value and internal ram area addition figure 12-5 dma channel control registers 0 to 2 (dchc0 to dchc2) deletion and addition of products in note 2 chapter 12 dma functions 14.2.1 (4) block diagram (port 0) addition 14.2.2 (3) block diagrams (port 1) addition 14.2.3 (3) block diagrams (port 2) addition 14.2.4 (3) block diagrams (port 3) addition 14.2.5 (1) functions of p4 and p5 pins modification of description 14.2.5 (3) block diagram (port 4, port 5) addition 14.2.6 (3) block diagram (port 6) addition 14.2.7 (2) block diagram (port 7, port 8) addition 14.2.8 (1) function of p9 pins modification of description 14.2.8 (3) block diagrams (port 9) addition 14.2.9 (3) block diagram (port 10) addition 14.2.10 (3) block diagrams (port 11) addition 14.2.11 (1) function of p12 pin deletion of description 14.2.11 (3) block diagram (port 12) addition 14.3 setting when port pin is used for alternate function addition chapter 14 port function 16.1.1 erase units addition 16.4 (3) csi0 + hs addition table 16-1 signal generation of dedicated flash programmer (pg-fp3) addition of csi0 + hs table 16-2 pins used by each serial interface addition of csi0 + hs 3rd edition table 16-3 list of communication systems addition of csi0 + hs chapter 16 flash memory ( pd70f3017a, 70f3017ay) addition of pd703014b, 703014by, 703015b, 703015by, 70f3015b, and 70f3015by deletion of pd703014agc, 703014aygc, 703015agc, and 703015aygc throughout addition of table 1-1 list of v850/sa1 products addition of description to the minimu m instruction execution time in 1.2 features deletion and addition of products in 1.4 ordering information deletion and addition of products in 1.5 pin configuration deletion of description in 1.6.2 (2) bus control unit (bcu) introduction addition of table 2-1 pin i/o buffer power supplies modification of description in table 2-2 operating states of pins in each operating mode modification of description in 2.3 (7) p60 to p65 (port 6) addition of 2.3 (13) clkout (clock out) addition and modification of description in 2.4 pin i/o circuits and recommended connection of unused pins 4th edition modification of 2.5 pin i/o circuits chapter 2 pin functions
appendix e revision history user?s manual u12768ej4v1ud 491 (6/7) edition major revision from pr evious edition applied to: addition of description to minimum instruction execution time in 3.1 features change of description in 3.2.2 (2) program status word (psw) modification of figure 3-16 recommended memory map addition of description in 3.4.8 peripheral i/o registers addition and modification of description in 3.4.9 specific registers chapter 3 cpu functions addition of description in 5.2.4 noise elimination of external interrupt request input pin addition of description in 5.2.5 edge detection function of external interrupt request input pin addition to cautions in 5.3.4 interrupt control register (xxicn) addition of caution in 5.3.5 in-service priority register (ispr) addition of 5.8.1 interrupt request valid timing after ei instruction addition of 5.9 bit manipulation instruction of interrupt control register during dma transfer chapter 5 interrupt/exce ption processing function modification of description in 6.1 (1) main clock oscillator modification of description in 6.1 (2) subclock oscillator modification of figure 6-1 clock generator addition to notes in 6.3.1 (1) processor clock control register (pcc) modification of description in 6.3.1 (1) (b) example of subclock operation main clock operation setup addition to notes and cautions in 6.3.1 (2) power save control register (psc) modification of description in 6.4.4 (1) settings and operating states addition of 6.6 notes on power save function chapter 6 clock generation function modification of caution in 7.1.3 (2) capture/compare registers 00, 10 (cr00, cr10) modification of caution in 7.1.3 (3) capture/compare registers 01, 11 (cr01, cr11) change of figure 7-27 data hold timing of capture register addition of 7.2.7 (6) (c) one-shot output function addition of 7.3.1 outline change of caution in 7.3.4 (2) 8-bit timer mode control registers 2 to 5 (tmc2 to tmc5) chapter 7 timer/counter function modification of description in 10.3.2 (3) iic clock select register 0 (iiccl0), iic function expansion register 0 (iicx0) addition of figures 10-25 to 10-29 chapter 10 serial interface function modification in 11.3 (1) a/d converter mode register (adm) addition of table 11-2 a/d conversion time selection addition of 11.6 how to read a/d converter characteristics table chapter 11 a/d converter change of description in 12.1 functions 4th edition deletion of 12.2 transfer completion interrupt request and addition of 12.2 features chapter 12 dma functions
appendix e revision history user?s manual u12768ej4v1ud 492 (7/7) edition major revision from pr evious edition applied to: addition of 12.3 configuration addition of figure 12-2 correspondence between dran setting value and internal ram (4 kb) addition of figure 12-3 correspondence between dran setting value and internal ram (8 kb) addition of 12.5 operations addition of 12.6 cautions chapter 12 dma functions addition of 13.2 features addition of 13.3 (2) output latch modification of description in 13.5 usage addition of description in 13.7 cautions chapter 13 real-time output function (rto) addition of table 14-1 pin i/o buffer power supplies addition of caution in 14.2.8 (1) function of p9 pins addition of 14.4 operation of port function chapter 14 port function addition of caution in chapter 16 flash memory change of description in 16.1.1 erasing unit addition of figure 16-1 wiring example of v850/sa1 flash writing adapter (fa100gc- 8eu) addition of table 16-1 wiring table of v850/sa1 flash writing adapter (fa100gc- 8eu) addition of figure 16-2 wiring example of v850/sa1 flash writing adapter (fa121f1- ea6) wiring example addition of table 16-2 wiring table of v850/sa1 flash writing adapter (fa121f1- ea6) addition of 16.7 flash memory programming by self-programming chapter 16 flash memory ( pd70f3017a, 70f3017ay) addition of chapter 17 electrical specifications chapter 17 electrical specifications addition of chapter 18 package drawings chapter 18 package drawings addition of chapter 19 recommended soldering conditions chapter 19 recommended soldering conditions addition of appendix a notes on target system design appendix a notes on target system design addition of description in appendix b register index appendix b register index 4th edition addition of appendix e revision history appendix e revision history

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